STMicroelectronics STM32WB55REV6TR

Overview

STM32WB55REV6TR from STMicroelectronics is a dual-core multiprotocol wireless 32-bit MCU integrating an Arm® Cortex®-M4 with FPU (64 MHz) and a dedicated Cortex®-M0+ for real-time radio processing, supporting Bluetooth® 5.4 and IEEE 802.15.4 PHY/MAC (Thread 1.3, Zigbee® 3.0), with -96 dBm BLE RX sensitivity, +6 dBm programmable TX power, and integrated balun. It targets ultra-low-power IoT edge nodes such as smart sensors and secure wireless gateways.

For engineers reviewing the STM32WB55REV6TR datasheet, STM32WB55REV6TR pinout, STM32WB55REV6TR application, or STM32WB55REV6TR equivalent, this page delivers verified RF performance specs, dual-CPU architecture details, low-power mode current values, flash/SRAM configuration, and package-specific pin mapping - all critical for BLE/802.15.4 system integration and regulatory-compliant RF design.

Technical Context

The device implements a tightly coupled dual-CPU architecture: the Cortex-M4 handles application logic and security (AES-256, PKA, RNG), while the Cortex-M0+ exclusively manages time-critical radio stack execution, enabling concurrent BLE and 802.15.4 operation without CPU contention. Inter-processor communication uses hardware IPCC and semaphores for deterministic latency.

RF subsystem includes a fully integrated 2.4 GHz transceiver with on-die balun, programmable output power in 1 dB steps (–20 to +6 dBm), and support for GATT caching, EATT, and advertising extensions. It complies with ETSI EN 300 328, FCC Part 15, and ARIB STD-T66, and supports external PA and IPD matching chips (e.g., MLPF-WB55-02E3).

Key Specifications

Pinout & Package

STM32WB55REV6TR is housed in a 129-ball UFBGA package (0.5 mm pitch, 7 × 7 mm body). Pin functions are validated per ST's DS11929 Rev 18, Section 4 ("Pinouts and pin description") and Table 16 ("STM32WB55xx pin and ball definitions"). Key RF pins include ANT (RF antenna interface), VDD_RF (dedicated RF supply), and VSS_RF (RF ground plane separation).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-core wireless MCU applications.

Compared with Nordic nRF52840 and TI CC2652R1F, STM32WB55REV6TR uniquely delivers certified Thread 1.3 + BLE 5.4 concurrency via hardware-isolated cores, integrated SMPS, and full hardware crypto suite - reducing BOM count by 4+ components and enabling single-chip certification for multi-protocol IoT gateways.

Availability

STM32WB55REV6TR is available at Aetrix Electronics and suitable for industrial wireless gateways, medical wearables, smart home sensors, and asset tracking tags requiring stable component supply across multi-year production cycles.

Supply support for STM32WB55REV6TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power ICs, sensors, and analog devices for industrial, automotive, and consumer markets.

This part belongs to the STM32WB wireless MCU product line, engineered specifically for secure, ultra-low-power, multi-protocol IoT endpoints and gateways - emphasizing regulatory-compliant RF integration, hardware-accelerated cryptography, and long-life battery operation.

FAQ

What is the maximum certified output power and regulatory compliance scope for STM32WB55REV6TR?

The device supports up to +6 dBm programmable TX power and is pre-certified for ETSI EN 300 328 (Europe), FCC CFR47 Part 15 (USA), and ARIB STD-T66 (Japan) when used with ST-recommended matching networks (e.g., MLPF-WB55-02E3) and layout guidelines. Final system-level certification remains the responsibility of the end equipment manufacturer.

Does STM32WB55REV6TR support over-the-air (OTA) updates for both application firmware and wireless protocol stacks?

Yes - it supports independent OTA updates for the application (running on Cortex-M4) and the BLE/802.15.4 protocol stacks (running on Cortex-M0+), using built-in bootloader with USB, USART, SPI, and I²C interfaces. Secure Firmware Installation (SFI) enforces cryptographic signature verification before stack activation.

How does the dual-CPU architecture prevent interference between application processing and radio timing?

The Cortex-M0+ executes only the time-critical radio stack (BLE/802.15.4 MAC/PHY) with hardware-protected memory and dedicated NVIC; the Cortex-M4 runs application code in separate address space. Communication occurs via IPCC mailboxes and hardware semaphores - eliminating software locks and guaranteeing sub-microsecond interrupt latency for radio events.

What are the key differences between STM32WB55REV6TR and STM32WB55CEU7 in terms of memory and package?

STM32WB55REV6TR features 1 MB flash and 256 KB SRAM in UFBGA129 (7 × 7 mm), while STM32WB55CEU7 offers 512 KB flash and 256 KB SRAM in WLCSP100 (3.14 × 3.14 mm). The REV6TR's larger flash enables concurrent dual-stack operation and field-upgradable secure boot images; its UFBGA package supports more I/Os and easier RF layout than WLCSP.