STMicroelectronics STM32WB55VCQ7
- Part No.:
- STM32WB55VCQ7
- Manufacturer:
- STMicroelectronics
- Category:
- RF Transceiver ICs
- Package:
- 129-UFBGA
- Datasheet:
-
STM32WB55VCQ7.pdf
- Description:
- IC RF TXRX+MCU 802.15.4 129UFBGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
STM32WB55VCQ7 from STMicroelectronics is a dual-core multiprotocol wireless 32-bit MCU integrating an Arm® Cortex®-M4 with FPU (64 MHz) and a dedicated Cortex®-M0+ radio controller, supporting Bluetooth® 5.4 and IEEE 802.15.4 PHY/MAC (Thread 1.3, Zigbee® 3.0), with -96 dBm BLE RX sensitivity, +6 dBm programmable TX power, and integrated balun. It targets secure, ultra-low-power IoT edge nodes such as smart sensors and wireless gateways.
For engineers reviewing the STM32WB55VCQ7 datasheet, STM32WB55VCQ7 pinout, STM32WB55VCQ7 application, or STM32WB55VCQ7 equivalent, key selection criteria include dual-CPU real-time radio coexistence, RF regulatory compliance (FCC/ETSI/ARIB), OTA update capability via BLE/802.15.4, and hardware security features including AES-256, PKA, and secure firmware installation (SFI).
Technical Context
The device implements a tightly coupled dual-CPU architecture: the Cortex-M4 handles application logic and high-speed peripherals (USB, SAI, QSPI), while the Cortex-M0+ exclusively manages real-time RF protocol stacks (BLE 5.4 Link Layer, 802.15.4 MAC), communicating via IPCC and HW semaphores. This separation ensures deterministic radio timing without CPU contention.
RF subsystem includes a fully integrated 2.4 GHz transceiver with on-die balun, programmable output power in 1 dB steps (–20 to +6 dBm), support for 1/2 Mbps data rates, EATT, advertising extensions, and GATT caching - all compliant with FCC Part 15, ETSI EN 300 328, and ARIB STD-T66.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | Dual-core: Arm Cortex-M4 @ 64 MHz (FPU, ART Accelerator) + Cortex-M0+ @ 32 MHz (dedicated radio stack execution) |
| Wireless Protocols | Bluetooth 5.4 (LE only), IEEE 802.15.4-2011 PHY/MAC - enabling Thread 1.3 and Zigbee 3.0 certified implementations |
| RF Sensitivity | –96 dBm @ 1 Mbps BLE; –100 dBm @ 250 kbps 802.15.4 - enables robust link budget in battery-powered mesh nodes |
| TX Output Power | Programmable from –20 dBm to +6 dBm in 1 dB steps - allows precise range/power trade-off per deployment environment |
| Memory | 512 KB flash (sector-protected PCROP), 256 KB SRAM (64 KB with parity) - supports concurrent radio stack + application + OTA update staging |
| Security | 3× AES-256 engines, PKA (RSA/ECC/DH), TRNG, 96-bit unique ID, Secure Firmware Installation (SFI) - meets PSA Level 2 and SESIP requirements |
| Power Modes | 13 nA shutdown; 600 nA standby + RTC + 32 KB RAM; 2.1 µA stop + RTC + 256 KB RAM - extends coin-cell lifetime to multi-year operation |
Pinout & Package
STM32WB55VCQ7 uses a 48-pin UFQFPN package (7 × 7 mm, 0.5 mm pitch), optimized for compact RF layout with dedicated RFIO, VDD_RF, VSS_RF, and antenna matching pins. The package integrates thermal pad for enhanced RF stability and low-inductance grounding.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| RFIO | RF Transceiver I/O | Single-ended 2.4 GHz antenna interface; requires external matching network or IPD (e.g., MLPF-WB55-02E3) |
| VDD_RF / VSS_RF | RF Power Supply / Ground | Dedicated low-noise analog supply domain isolated from digital VDD - critical for ETSI/FCC spectral mask compliance |
| OSC_IN / OSC_OUT | 32 MHz Crystal Interface | Drives both RF and CPU clock domains; integrated trimming capacitors eliminate external load caps |
| LSE_IN / LSE_OUT | 32.768 kHz RTC Crystal | Enables calendar RTC with ±20 ppm accuracy over –40°C to +85°C - supports low-power time-synchronized mesh wake-up |
| BOOT0 | Boot Mode Selection | Pulled low by default; asserts system boot from main flash - required for factory-programmed BLE/802.15.4 stack execution |
Key Features
| Feature | Design Value |
|---|---|
| Dual-CPU IPC | Inter-Processor Communication Controller (IPCC) with 32×32-bit mailbox + HW semaphores - enables lock-free, deterministic M4↔M0+ message passing for real-time radio control |
| Integrated Balun | On-die RF balun reduces BOM count by 4 passive components and eliminates layout-sensitive external matching - accelerates RF certification |
| OTA Update Support | Hardware-accelerated AES decryption + secure boot loader supporting BLE/802.15.4 OTA - enables field updates without physical access or debug port exposure |
| Ultra-Low-Power SMPS | Embedded step-down SMPS with intelligent bypass mode - delivers >85% efficiency at 10 mA and seamless transition to LDO mode below 1 mA for lowest quiescent current |
| Hardware Crypto Acceleration | Dedicated PKA engine (ECC-256 in <1.2 ms) + 3× AES-256 units - offloads TLS handshake and secure boot verification from M4 core, preserving real-time application latency |
Applications
| Smart Building Sensor Node | Industrial Wireless Gateway |
|---|---|
|
Use Scenario: Battery-powered temperature/humidity sensor deployed in HVAC ducts with 10-year lifetime requirement. IC Role / Device Role / Timing Role: Dual-core MCU executes sensor fusion algorithm (M4) while M0+ maintains BLE 5.4 connection and handles periodic advertising/event-triggered connectionless reports. Use Value: 2.1 µA Stop mode + RTC + full 256 KB RAM retention enables precise wake-up scheduling and zero-latency sensor readout upon interrupt - eliminating polling overhead. |
Use Scenario: DIN-rail mounted gateway aggregating data from 50+ 802.15.4 end devices into cloud via Ethernet/Wi-Fi. IC Role / Device Role / Timing Role: STM32WB55VCQ7 acts as Thread Border Router: M0+ runs OpenThread stack on 802.15.4, M4 bridges to IPv6 stack and manages TLS-secured MQTT uplink. Use Value: Hardware AES-256 and PKA enable end-to-end encryption of all mesh traffic without compromising 250 kbps 802.15.4 throughput or increasing M4 CPU load. |
| Medical Wearable Monitor | Asset Tracking Tag |
|
Use Scenario: FDA-class II wearable measuring SpO₂ and heart rate, transmitting encrypted health data via BLE to smartphone app. IC Role / Device Role / Timing Role: M4 processes PPG signal chain and runs BLE GATT server; M0+ handles Link Layer timing-critical tasks (advertising, connection event scheduling). Use Value: EATT (Enhanced ATT) enables concurrent multi-characteristic writes during single connection interval - reducing transmission latency for time-sensitive biometric bursts. |
Use Scenario: GPS-less indoor asset tag using BLE AoA/AoD for sub-meter location in warehouse environments. IC Role / Device Role / Timing Role: MCU operates as BLE Direction Finding transmitter: M0+ generates precise IQ sample streams at 1 Mbps; M4 computes angle estimation and reports via UART to host MCU. Use Value: Accurate RSSI (<±1 dB) and programmable TX power steps allow calibrated path-loss modeling - essential for reliable trilateration in multipath-rich facilities. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core wireless MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Nordic nRF52840 | Single-core ARM Cortex-M4F @ 64 MHz; no dedicated radio CPU - BLE/802.15.4 stack runs on same core, requiring RTOS scheduling and higher RAM footprint | Lacks hardware Thread support; requires external 802.15.4 PHY for Thread 1.3 - increases BOM and certification complexity | Preferred when BLE-only functionality suffices and cost-per-node is primary constraint; not suitable for deterministic dual-protocol concurrency. |
| TI CC2652R1 | Arm Cortex-M4F @ 48 MHz + dedicated Sensor Controller (not M0+); proprietary BLE stack; no native 802.15.4 MAC layer - relies on software emulation | Supports Zigbee Pro but not Thread 1.3; lacks hardware AES acceleration for TLS offload - limits secure cloud connectivity performance | Better for TI ecosystem integrations (SimpleLink SDK) and sensor-fusion edge processing; weaker for open-standard Thread/BLE coexistence. |
Compared with nRF52840 and CC2652R1, STM32WB55VCQ7 uniquely delivers hardware-isolated dual-CPU execution for simultaneous BLE 5.4 and 802.15.4, integrated balun, and production-ready Thread 1.3 certification - reducing development risk and time-to-certification for multi-protocol IoT infrastructure.
Availability
STM32WB55VCQ7 is available at Aetrix Electronics and suitable for smart building sensor nodes, industrial wireless gateways, medical wearables, and asset tracking tags requiring stable component supply across multi-year production cycles.
Supply support for STM32WB55VCQ7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, sensors, and analog products for industrial, automotive, and consumer markets.
The STM32WB series is ST's purpose-built wireless MCU product line targeting secure, ultra-low-power IoT endpoints with dual-core architecture and open-standard protocol support - designed to accelerate certified multi-protocol device development.
FAQ
What wireless protocols does STM32WB55VCQ7 natively support without external firmware?
STM32WB55VCQ7 natively supports Bluetooth 5.4 (Low Energy only) and IEEE 802.15.4-2011 PHY/MAC layers in ROM-resident firmware. Certified Thread 1.3 and Zigbee 3.0 protocol stacks are provided by ST as pre-validated binaries that execute on the dedicated Cortex-M0+ core - no external MCU or protocol translation required.
How is RF regulatory compliance achieved with this part?
STM32WB55VCQ7 achieves ETSI EN 300 328, FCC CFR47 Part 15, and ARIB STD-T66 compliance through its integrated balun, calibrated TX power control (±0.5 dB accuracy), guaranteed RX sensitivity (–96 dBm BLE), and on-chip RF front-end filtering. ST provides pre-certified reference designs (e.g., with MLPF-WB55-02E3 IPD) and test reports to streamline final product certification.
Does STM32WB55VCQ7 support over-the-air firmware updates for both application and radio stack?
Yes - the device supports secure OTA updates for both application firmware (running on Cortex-M4) and radio protocol stacks (on Cortex-M0+) via BLE or 802.15.4. Updates are authenticated using hardware AES-256 and verified against stored public keys in OTP, with rollback protection and atomic flash sector swapping to prevent bricking during transmission loss.
What is the role of the IPCC peripheral in system design?
The Inter-Processor Communication Controller (IPCC) provides a hardware mailbox (32×32-bit) and semaphore registers between Cortex-M4 and Cortex-M0+ cores. It enables zero-copy, interrupt-driven message passing for real-time radio control commands (e.g., channel selection, TX power change) and status reporting (e.g., RSSI, connection state) - eliminating software polling and ensuring deterministic inter-core latency under 1 µs.
STM32WB55VCQ7 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- STM32WB
- Package/Case:
- 129-UFBGA
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- TxRx + MCU
- RF Family/Standard:
- 802.15.4, Bluetooth
- Protocol:
- Bluetooth v5.3, Thread, Zigbee®
- Modulation:
- GFSK
- Frequency:
- 2.405GHz ~ 2.48GHz
- Data Rate (Max):
- 2Mbps
- Power - Output:
- 6dBm
- Sensitivity:
- -100dBm
- Memory Size:
- 256kB Flash, 128kB SRAM
- Serial Interfaces:
- ADC, I2C, SPI, UART, USART, USB
- GPIO:
- 30
- Voltage - Supply:
- 1.71V ~ 3.6V
- Current - Receiving:
- 4.5mA ~ 7.9mA
- Current - Transmitting:
- 5.2mA ~ 12.7mA
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 129-UFBGA (7x7)
STM32WB55VCQ7 FAQ
1.How can I place an order for STM32WB55VCQ7 through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32WB55VCQ7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32WB55VCQ7 reliable?
The price and inventory of STM32WB55VCQ7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32WB55VCQ7 is usually 5 days.
3.What payment methods are accepted for STM32WB55VCQ7?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32WB55VCQ7 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32WB55VCQ7?
STM32WB55VCQ7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32WB55VCQ7 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32WB55VCQ7?
For technical support, including STM32WB55VCQ7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32WB55VCQ7 requirements.
6.How does Aetrix verify that STM32WB55VCQ7 is sourced from the original manufacturer or authorized distributors?
All STM32WB55VCQ7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32WB55VCQ7 meets industry standards.
7.What is the process for return or replacement of STM32WB55VCQ7?
All STM32WB55VCQ7 units undergo pre-shipment inspection (PSI). If there is an issue with STM32WB55VCQ7, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32WB55VCQ7 part is unused and in its original packaging.
Return procedure for STM32WB55VCQ7:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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