STMicroelectronics STM32WB55VEQ6TR
- Part No.:
- STM32WB55VEQ6TR
- Manufacturer:
- STMicroelectronics
- Category:
- RF Transceiver ICs
- Package:
- 129-UFBGA
- Datasheet:
-
STM32WB55VEQ6TR.pdf
- Description:
- IC RF TXRX+MCU BLE 129UFBGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
STM32WB55VEQ6TR from STMicroelectronics is a dual-core, multiprotocol wireless 32-bit MCU integrating an Arm® Cortex®-M4 with FPU (64 MHz) and a dedicated Cortex®-M0+ for real-time radio processing. It supports Bluetooth® 5.4 and IEEE 802.15.4 PHY/MAC (Thread 1.3/Zigbee® 3.0), delivers -96 dBm RX sensitivity at 1 Mbps BLE, +6 dBm programmable TX power, and operates from 1.71–3.6 V in industrial temperature range (-40 °C to 105 °C). It targets secure, ultra-low-power IoT edge nodes such as smart sensors and wireless gateways.
For engineers reviewing the STM32WB55VEQ6TR datasheet, STM32WB55VEQ6TR pinout, STM32WB55VEQ6TR application, or STM32WB55VEQ6TR equivalent, key selection criteria include dual-CPU architecture for concurrent application/radio execution, integrated SMPS for sub-µA low-power modes (600 nA Standby + RTC + 32 KB RAM), RF regulatory compliance (FCC/ETSI/ARIB), and hardware crypto acceleration (AES-256, PKA, RNG).
Technical Context
The device implements a tightly coupled dual-CPU architecture: the Cortex-M4 handles application logic and high-performance peripherals (USB FS, SAI, QSPI), while the Cortex-M0+ exclusively manages time-critical radio stack operations via IPCC interprocessor communication. This separation enables deterministic BLE/802.15.4 timing without CPU contention.
Its RF subsystem integrates a 2.4 GHz transceiver with on-die balun, supporting 1/2 Mbps data rates, EATT, advertising extensions, and GATT caching. The embedded SMPS features intelligent bypass mode, and the security subsystem includes PCROP flash protection, secure firmware installation (SFI), and hardware-accelerated ECC/RSA.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | Dual-core: Arm Cortex-M4 @ 64 MHz (FPU, ART Accelerator) + Cortex-M0+ @ 32 MHz (dedicated radio layer) |
| Wireless Protocols | Bluetooth 5.4 (LE), IEEE 802.15.4-2011 (PHY/MAC), Thread 1.3, Zigbee 3.0 - all supported concurrently in single chip |
| RF Performance | RX sensitivity: -96 dBm (BLE 1 Mbps), -100 dBm (802.15.4); TX output: programmable up to +6 dBm in 1 dB steps |
| Power Efficiency | 600 nA Standby mode (RTC + 32 KB RAM), 2.1 µA Stop mode (RTC + 256 KB RAM), <53 µA/MHz active (RF + SMPS on) |
| Memory | 512 KB flash (sector-protected PCROP), 256 KB SRAM (64 KB with parity), 1 KB OTP, Quad-SPI XIP interface |
| Security | 3× AES-256 engines, PKA (RSA/ECC/DH), TRNG, 96-bit unique ID, secure boot, SFI for radio stack integrity |
| Package & Pins | UFQFPN48 (7 × 7 mm, 0.4 mm pitch), 72 fast I/Os (70 × 5 V-tolerant), 32 kHz LSE crystal support for RTC |
Pinout & Package
STM32WB55VEQ6TR is housed in a 48-pin Ultra-Fine Pitch Quad Flat No-lead (UFQFPN48) package with 0.4 mm pitch and 7 × 7 mm body size, optimized for compact PCB layouts and RF performance stability.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD | Main power supply | 1.71–3.6 V input for digital/analog domains; connects to internal SMPS or LDO |
| VSS | Ground reference | Digital ground plane connection; requires low-inductance layout for RF stability |
| RF_IO | RF transceiver antenna interface | Differential RF port (balanced); connects directly to integrated balun or external matching network |
| OSC_IN / OSC_OUT | 32 MHz crystal oscillator terminals | Drives main system clock and radio timing; integrated trimming capacitors reduce BOM count |
| LSE_IN / LSE_OUT | 32.768 kHz RTC crystal terminals | Enables precise real-time clock operation during ultra-low-power Stop/Standby modes |
| BOOT0 | Boot mode selection | High at reset selects system memory bootloader; used for UART/SPI/I2C/USB firmware update |
Key Features
| Feature | Design Value |
|---|---|
| Dual-CPU Radio Architecture | Hardware-isolated Cortex-M0+ executes BLE/802.15.4 stack independently, eliminating RTOS scheduling latency and guaranteeing sub-millisecond radio timing |
| Integrated RF Balun | Eliminates discrete balun components, reduces PCB area by ≥20%, improves impedance matching repeatability across production units |
| Ultra-Low-Power SMPS | Embedded step-down converter with intelligent bypass mode cuts active current to <53 µA/MHz and enables 600 nA Standby with full RTC + RAM retention |
| Hardware Crypto Engine | Three independent AES-256 accelerators + PKA co-processor enable concurrent encryption of application, BLE, and 802.15.4 traffic without CPU overhead |
| Secure Firmware Installation (SFI) | Verifies cryptographic signature of over-the-air (OTA) radio stack updates before execution, preventing unauthorized firmware injection |
Applications
| Smart Building Sensor Node | Industrial Wireless Gateway |
|---|---|
Use Scenario: Battery-powered temperature/humidity/motion sensor deployed in HVAC ducts or lighting fixtures with multi-year battery life. IC Role / Device Role / Timing Role: Primary system-on-chip executing sensor fusion, BLE advertising, and 802.15.4 mesh routing; Cortex-M0+ handles packet timing and channel hopping per IEEE 802.15.4 standard. Use Value: 600 nA Standby + RTC enables accurate wake-up scheduling; integrated balun and SMPS reduce bill-of-materials and extend battery life beyond 5 years. |
Use Scenario: Edge gateway aggregating data from 50+ BLE/Thread/Zigbee end devices in factory automation, forwarding to cloud via Ethernet or cellular. IC Role / Device Role / Timing Role: Dual-CPU orchestrates concurrent protocol stacks (BLE for commissioning, Thread for mesh, Zigbee for legacy compatibility) with deterministic latency. Use Value: Hardware IPC (IPCC) and semaphores prevent resource contention; 512 KB flash stores multiple certified protocol stacks and OTA update images. |
| Medical Wearable Transmitter | Asset Tracking Tag |
Use Scenario: CE-certified wearable patch transmitting ECG/SpO₂ data via BLE to smartphone and 802.15.4 to local hub, operating under strict power and safety constraints. IC Role / Device Role / Timing Role: Secure application processor (Cortex-M4) runs medical algorithm and encrypts data; Cortex-M0+ enforces BLE privacy features (Resolvable Private Address) and RSSI-based proximity detection. Use Value: AES-256 + PKA + TRNG meet IEC 62304 Class C security requirements; 2.1 µA Stop mode preserves RAM state during intermittent sensing cycles. |
Use Scenario: GPS-denied indoor/outdoor asset tag using BLE direction finding (AoA/AoD) and 802.15.4 geofencing, powered by coin cell. IC Role / Device Role / Timing Role: Real-time radio controller (Cortex-M0+) manages BLE angle estimation packets and 802.15.4 beacon intervals with microsecond-level timing accuracy. Use Value: -96 dBm RX sensitivity extends BLE range to 120 m line-of-sight; programmable +6 dBm TX enables reliable link budget in metal-rich environments. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core wireless MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Nordic nRF52840 DK | Single-core ARM Cortex-M4F (64 MHz); no dedicated radio CPU; BLE 5.0 only (no 802.15.4/Thread/Zigbee native stack) | Limited to BLE-centric designs; requires software-based protocol bridging for multi-protocol use cases | Select when BLE-only functionality suffices and cost sensitivity outweighs need for concurrent multi-protocol support |
| TI CC2652R1F | Arm Cortex-M4F + dedicated radio controller (not Cortex-M0+); supports BLE 5.1, Zigbee 3.0, and 802.15.4 but lacks Thread 1.3 certification and hardware PKA | Requires external crypto IC for full TLS/ECC implementation; lower RF sensitivity (-96 dBm BLE, no 802.15.4 spec sheet value) | Prefer for legacy TI ecosystem integration or where SimpleLink SDK familiarity reduces development time |
Compared with Nordic nRF52840 and TI CC2652R1F, STM32WB55VEQ6TR uniquely delivers native Thread 1.3 + Zigbee 3.0 + BLE 5.4 concurrency via dual-CPU isolation, integrated PKA for ECC acceleration, and -100 dBm 802.15.4 RX sensitivity-enabling robust, standards-compliant mesh deployments without external co-processors.
Availability
STM32WB55VEQ6TR is available at Aetrix Electronics and suitable for smart building sensor nodes, industrial wireless gateways, medical wearables, and asset tracking tags requiring stable component supply, long-term lifecycle assurance, and full regulatory compliance (FCC/ETSI/ARIB).
Supply support for STM32WB55VEQ6TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, analog ICs, power management, and MEMS sensors for industrial, automotive, and consumer markets.
The STM32WB series is ST's purpose-built wireless MCU product line targeting secure, ultra-low-power IoT endpoints-designed to unify BLE, Thread, and Zigbee protocol stacks on a single chip with hardware-enforced security and energy efficiency.
FAQ
What wireless protocols does STM32WB55VEQ6TR support natively in firmware?
STM32WB55VEQ6TR supports Bluetooth 5.4 (including LE Audio-ready features), IEEE 802.15.4-2011 PHY/MAC, Thread 1.3, and Zigbee 3.0-all certified and delivered as pre-validated, memory-resident stacks. The dual-CPU architecture allows simultaneous operation: Cortex-M0+ executes the radio stack while Cortex-M4 runs application code, enabling true concurrent multi-protocol behavior without time-slicing overhead.
How does the integrated SMPS improve power efficiency compared to external regulators?
The embedded SMPS achieves <53 µA/MHz active current and enables 600 nA Standby mode (RTC + 32 KB RAM) by eliminating external inductor losses, PCB trace resistance, and regulator quiescent current. Its intelligent bypass mode automatically switches to LDO operation during low-current states, reducing switching noise near sensitive RF/analog circuits while maintaining regulation accuracy across 1.71–3.6 V input range.
Is STM32WB55VEQ6TR qualified for industrial temperature operation?
Yes. STM32WB55VEQ6TR is rated for -40 °C to +105 °C ambient operating temperature, validated per ST's industrial qualification standards (AEC-Q100 not required, but meets extended temp reliability testing). This rating applies across all low-power modes and RF performance specifications, including -96 dBm RX sensitivity and +6 dBm TX output, ensuring consistent operation in harsh environments like factory floors or outdoor enclosures.
What development tools and debug interfaces are supported?
STM32WB55VEQ6TR supports Serial Wire Debug (SWD) and JTAG via dedicated pins, plus Embedded Trace Macrocell (ETM) for instruction-level tracing. ST's STM32CubeWB ecosystem provides full HAL/LL drivers, pre-certified protocol stacks, and the STM32CubeMX configuration tool. Debugging is compatible with ST-LINK/V2-1, J-Link, and CMSIS-DAP probes-no proprietary hardware required.
STM32WB55VEQ6TR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 129-UFBGA
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- -
- Type:
- TxRx + MCU
- RF Family/Standard:
- Bluetooth
- Protocol:
- Bluetooth v5.3, Zigbee®
- Modulation:
- -
- Frequency:
- 2.4GHz
- Data Rate (Max):
- 2Mbps
- Power - Output:
- 6dBm
- Sensitivity:
- -100dBm
- Memory Size:
- 1MB Flash, 512kB SRAM
- Serial Interfaces:
- GPIO, I2C, IrDA, JTAG, PWM, SPI, UART, USART, USB
- GPIO:
- 72
- Voltage - Supply:
- 1.71V ~ 3.6V
- Current - Receiving:
- 4.5mA ~ 9.2mA
- Current - Transmitting:
- 4.5mA ~ 12.7mA
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 129-UFBGA (7x7)
STM32WB55VEQ6TR FAQ
1.How can I place an order for STM32WB55VEQ6TR through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32WB55VEQ6TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32WB55VEQ6TR reliable?
The price and inventory of STM32WB55VEQ6TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32WB55VEQ6TR is usually 5 days.
3.What payment methods are accepted for STM32WB55VEQ6TR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32WB55VEQ6TR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32WB55VEQ6TR?
STM32WB55VEQ6TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32WB55VEQ6TR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32WB55VEQ6TR?
For technical support, including STM32WB55VEQ6TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32WB55VEQ6TR requirements.
6.How does Aetrix verify that STM32WB55VEQ6TR is sourced from the original manufacturer or authorized distributors?
All STM32WB55VEQ6TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32WB55VEQ6TR meets industry standards.
7.What is the process for return or replacement of STM32WB55VEQ6TR?
All STM32WB55VEQ6TR units undergo pre-shipment inspection (PSI). If there is an issue with STM32WB55VEQ6TR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32WB55VEQ6TR part is unused and in its original packaging.
Return procedure for STM32WB55VEQ6TR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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