STMicroelectronics STM32WB55VEY6TR
- Part No.:
- STM32WB55VEY6TR
- Manufacturer:
- STMicroelectronics
- Category:
- RF Transceiver ICs
- Package:
- 100-UFBGA, WLCSP
- Datasheet:
-
STM32WB55VEY6TR.pdf
- Description:
- IC RF TXRX+MCU 802.15.4 100WLCSP
- Quantity:
- Payment:

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Product details
Overview
STM32WB55VEY6TR from STMicroelectronics is a dual-core 32-bit wireless MCU integrating an Arm® Cortex®-M4 with FPU (64 MHz) and a dedicated Cortex®-M0+ radio controller, supporting Bluetooth® 5.4 and IEEE 802.15.4 PHY/MAC (Thread 1.3/Zigbee® 3.0), with -96 dBm BLE RX sensitivity, +6 dBm programmable TX power, and ultra-low-power operation down to 13 nA in shutdown mode. It targets secure, battery-powered IoT edge nodes requiring concurrent application processing and certified RF stack execution.
For engineers reviewing the STM32WB55VEY6TR datasheet, STM32WB55VEY6TR pinout, STM32WB55VEY6TR application, or STM32WB55VEY6TR equivalent, key selection criteria include dual-CPU real-time radio coexistence, integrated SMPS for <53 µA/MHz active efficiency, hardware AES-256/PKA security, OTA update capability via BLE/802.15.4, and UFBGA129 package compatibility with RF layout constraints.
Technical Context
The device implements a tightly coupled dual-CPU architecture: the M4 executes application firmware while the M0+ handles time-critical radio protocol stack tasks via IPCC interprocessor messaging and hardware semaphores-enabling deterministic BLE/802.15.4 timing without CPU contention. The RF subsystem includes an integrated balun, RSSI-based closed-loop TX power control, and support for advertising extensions and EATT.
Power management combines an embedded SMPS with intelligent bypass mode, five-level BOR, and seven low-power modes-including Stop mode at 2.1 µA with RTC + 256 KB RAM retention-optimized for intermittent sensor wake-up and long-life coin-cell operation. Clocking integrates 32 MHz crystal oscillator with trimming capacitors, dual PLLs, and auto-trimmed MSI for ±0.25% accuracy.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | Dual-core: Arm Cortex-M4 @ 64 MHz (FPU, ART Accelerator) + Cortex-M0+ @ 32 MHz (dedicated radio layer) |
| Wireless Protocols | Bluetooth 5.4 (LE), IEEE 802.15.4-2011 PHY/MAC - enables Thread 1.3 and Zigbee 3.0 certified stacks |
| RF Sensitivity | -96 dBm @ 1 Mbps BLE / -100 dBm @ 802.15.4 - ensures robust link budget in noisy 2.4 GHz environments |
| TX Output Power | Programmable up to +6 dBm in 1 dB steps - supports regulatory compliance across ETSI/FCC/ARIB domains |
| Memory | 512 KB Flash (sector PCROP protection), 256 KB SRAM (64 KB with parity) - isolates radio stack from app code |
| Low-Power Modes | 13 nA Shutdown, 600 nA Standby + RTC + 32 KB RAM, 2.1 µA Stop + RTC + 256 KB RAM - extends battery life to years |
| Security | 3× AES-256 engines, PKA (RSA/ECC/DH), TRNG, 96-bit unique ID, SFI for secure radio stack installation |
| Package | UFBGA129, 0.5 mm pitch, 7 × 7 mm - compact RF-optimized footprint with ground plane integrity |
Pinout & Package
STM32WB55VEY6TR uses the UFBGA129 package (7 × 7 mm, 0.5 mm pitch), designed for high-density RF PCB layouts with dedicated RFIO, VDDRF, and ground ball patterns to minimize noise coupling. Pin functions are validated per ST's DS11929 Rev 18 Table 16 (STM32WB55xx pin definitions).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| RFIO | 2.4 GHz RF transceiver I/O | Differential RF port requiring 50 Ω matching network; connects directly to antenna or IPD filter (e.g., MLPF-WB55-02E3) |
| VDDRF | RF power supply | Separate 1.2 V supply for RF block; decoupling critical for EMI suppression and RX sensitivity stability |
| VBAT | Backup power supply | Enables RTC and 32 KB backup RAM retention during main power loss - supports tamper detection and calendar functions |
| NRST | Active-low reset input | Asynchronous reset pin with internal pull-up; compatible with external push-button or supervisor IC assertion |
| BOOT0 | Boot mode selection | Configures boot source (system memory, flash, or SRAM); sampled at power-on reset to enable DFU or debug recovery |
| PA13/PA14 | SWD debug interface | Serial Wire Debug pins (SWDIO/SWCLK); allow full JTAG/SWD access to both M4 and M0+ cores for co-debugging |
Key Features
| Feature | Design Value |
|---|---|
| Dual-CPU IPC | Inter-Processor Communication Controller (IPCC) with 32×32-bit mailbox registers enables zero-copy, interrupt-driven data exchange between M4 and M0+ |
| Hardware Security | Secure Firmware Installation (SFI) enforces cryptographic signature verification before loading BLE/802.15.4 stack into protected flash sectors |
| RF Integration | Integrated balun eliminates external matching components - reduces BOM count and layout sensitivity for 2.4 GHz operation |
| Power Efficiency | SMPS with intelligent bypass mode automatically switches to LDO under light load - maintains >85% efficiency across 10 µA–100 mA range |
| OTA Update | Over-the-air update engine supports atomic firmware swap with rollback on CRC failure - ensures field reliability without physical access |
| Analog Peripherals | 12-bit ADC @ 4.26 Msps with hardware oversampling to 16-bit resolution - enables high-fidelity sensor acquisition in low-power modes |
Applications
| Smart Home Sensor Hub | Industrial Wireless Node |
|---|---|
Use Scenario: Battery-powered temperature/humidity/motion sensor aggregating data from multiple analog/digital sensors and transmitting via BLE to gateway. IC Role / Device Role / Timing Role: Dual-core orchestrates sensor polling (M4), runs BLE GATT server (M0+), and manages low-power scheduling with 2.1 µA Stop mode + RTC wake-up every 5 seconds. Use Value: 10-year coin-cell life enabled by 13 nA shutdown and RSSI-based adaptive TX power scaling. | Use Scenario: DIN-rail mounted predictive maintenance node monitoring vibration, current, and temperature in factory machinery using 802.15.4 mesh networking. IC Role / Device Role / Timing Role: Executes Thread 1.3 border router logic (M4) while M0+ handles MAC-layer CSMA/CA, frame filtering, and ACK timing with <1 µs jitter. Use Value: Certified 802.15.4 PHY/MAC compliance ensures interoperability with third-party Thread devices and avoids costly RF re-certification. |
| Medical Wearable | Asset Tracking Tag |
Use Scenario: FDA-classified wearable measuring ECG and SpO₂, transmitting encrypted health data via BLE to smartphone with HIPAA-compliant pairing. IC Role / Device Role / Timing Role: M4 runs signal processing algorithms and TLS stack; M0+ handles BLE Link Layer encryption (AES-CCM) and EATT for multi-attribute writes. Use Value: On-chip PKA accelerates ECC key generation for secure pairing; TRNG feeds cryptographic RNG - meets IEC 62304 security requirements. | Use Scenario: GPS-denied indoor logistics tag reporting location via BLE beacons and ambient light/temperature for environmental context. IC Role / Device Role / Timing Role: Uses LPUART + I²C for sensor fusion, SAI for audio alert, and ultra-low-power timers to schedule beacon scanning every 30 s in Stop mode. Use Value: 600 nA Standby + RTC + 32 KB RAM retains last known position and sensor history during deep sleep - enables instant wake-on-motion detection. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core wireless MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Nordic nRF52840 DK | Single-core ARM Cortex-M4F @ 64 MHz; no dedicated radio CPU - BLE/802.15.4 stack runs on same core with RTOS scheduling overhead | Limited deterministic timing for concurrent BLE + Thread; higher CPU utilization impacts sensor processing latency | Prefer when cost-sensitive designs accept software-managed radio concurrency and lack need for hardware-isolated security engines |
| TI CC2652R1 | Arm Cortex-M4F @ 48 MHz + dedicated Sensor Controller (16-bit RISC); supports BLE 5.0 and IEEE 802.15.4 but not Thread 1.3 or Zigbee 3.0 out-of-box | Requires TI's Z-Stack or BLE-Stack licensing; lacks integrated SMPS and has higher active current (6.9 mA RX vs 4.5 mA) | Prefer when leveraging TI's SimpleLink SDK ecosystem and prioritizing sub-GHz coexistence over 2.4 GHz multi-protocol certification |
Compared with Nordic nRF52840 and TI CC2652R1, STM32WB55VEY6TR uniquely delivers hardware-isolated radio execution, Thread 1.3/Zigbee 3.0 certification readiness, and lowest active RX current - making it optimal for battery-constrained, multi-protocol, security-critical edge nodes where deterministic timing and regulatory compliance are non-negotiable.
Availability
STM32WB55VEY6TR is available at Aetrix Electronics and suitable for smart home sensor hubs, industrial wireless nodes, medical wearables, and asset tracking tags requiring stable component supply across multi-year production cycles.
Supply support for STM32WB55VEY6TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, specializing in microcontrollers, power management, sensors, and automotive ICs with strong emphasis on industrial and IoT innovation.
The STM32WB series is ST's wireless MCU product line engineered specifically for secure, ultra-low-power, multi-protocol (BLE/802.15.4) edge devices - combining dual-core processing, hardware crypto acceleration, and RF integration in single-die solutions.
FAQ
What development tools support dual-core debugging of STM32WB55VEY6TR?
STM32CubeIDE v1.14+ provides native dual-core debugging via SWD, allowing simultaneous breakpoints, register inspection, and memory view across both Cortex-M4 and Cortex-M0+ cores. ST-LINK/V3 supports trace capture through ETM and ITM interfaces, and the STM32WB5MM-DK discovery kit includes onboard debugger with full IPCC visibility for inter-core message tracing.
Does STM32WB55VEY6TR require external RF front-end components?
No - the device integrates a balun and supports direct connection to PCB antennas or chip antennas. For optimized performance, ST recommends companion IPD filters like MLPF-WB55-02E3 to meet ETSI/FCC radiated emission limits without discrete matching networks. External PA is optional and supported via dedicated RF output control pins.
How is secure firmware update implemented on STM32WB55VEY6TR?
Secure firmware updates use Secure Firmware Installation (SFI), which validates ECDSA signatures of OTA images using the on-chip PKA engine before writing to protected flash sectors. The process enforces image authenticity, integrity, and version rollback prevention - all executed in ROM bootloader without exposing private keys to application code.
What is the maximum operating temperature for STM32WB55VEY6TR in UFBGA129 package?
The STM32WB55VEY6TR in UFBGA129 package is rated for operation from –40 °C to +105 °C ambient temperature (industrial grade), verified per ST's DS11929 Rev 18 Section 6.3.2. Thermal derating begins above 85 °C ambient when operating at maximum CPU/RF frequency, requiring PCB thermal vias and copper pour per ST AN5028 layout guidelines.
STM32WB55VEY6TR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- STM32WB
- Package/Case:
- 100-UFBGA, WLCSP
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- TxRx + MCU
- RF Family/Standard:
- 802.15.4, Bluetooth
- Protocol:
- Bluetooth v5.3, Thread, Zigbee®
- Modulation:
- GFSK
- Frequency:
- 2.405GHz ~ 2.48GHz
- Data Rate (Max):
- 2Mbps
- Power - Output:
- 6dBm
- Sensitivity:
- -100dBm
- Memory Size:
- 512kB Flash, 256kB SRAM
- Serial Interfaces:
- ADC, I2C, SPI, UART, USART, USB
- GPIO:
- 72
- Voltage - Supply:
- 1.71V ~ 3.6V
- Current - Receiving:
- 4.5mA ~ 7.9mA
- Current - Transmitting:
- 5.2mA ~ 12.7mA
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 100-WLCSP (4.4x4.38)
STM32WB55VEY6TR FAQ
1.How can I place an order for STM32WB55VEY6TR through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32WB55VEY6TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32WB55VEY6TR reliable?
The price and inventory of STM32WB55VEY6TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32WB55VEY6TR is usually 5 days.
3.What payment methods are accepted for STM32WB55VEY6TR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32WB55VEY6TR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32WB55VEY6TR?
STM32WB55VEY6TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32WB55VEY6TR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32WB55VEY6TR?
For technical support, including STM32WB55VEY6TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32WB55VEY6TR requirements.
6.How does Aetrix verify that STM32WB55VEY6TR is sourced from the original manufacturer or authorized distributors?
All STM32WB55VEY6TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32WB55VEY6TR meets industry standards.
7.What is the process for return or replacement of STM32WB55VEY6TR?
All STM32WB55VEY6TR units undergo pre-shipment inspection (PSI). If there is an issue with STM32WB55VEY6TR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32WB55VEY6TR part is unused and in its original packaging.
Return procedure for STM32WB55VEY6TR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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