STMicroelectronics STM32WB55VEY7TR
- Part No.:
- STM32WB55VEY7TR
- Manufacturer:
- STMicroelectronics
- Category:
- RF Transceiver ICs
- Package:
- 100-UFBGA, WLCSP
- Datasheet:
-
STM32WB55VEY7TR.pdf
- Description:
- IC RF TXRX+MCU 802.15.4 100WLCSP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
STM32WB55VEY7TR from STMicroelectronics is a dual-core multiprotocol wireless 32-bit MCU integrating an Arm® Cortex®-M4 with FPU (64 MHz) and a dedicated Cortex®-M0+ for real-time radio processing, supporting Bluetooth® 5.4 and IEEE 802.15.4 PHY/MAC (Thread 1.3, Zigbee® 3.0), with -96 dBm BLE RX sensitivity, +6 dBm programmable TX power, and ultra-low-power operation down to 13 nA in shutdown mode. It targets secure, battery-powered IoT edge nodes requiring concurrent application execution and certified RF compliance (FCC/ETSI/ARIB).
For engineers reviewing the STM32WB55VEY7TR datasheet, STM32WB55VEY7TR pinout, STM32WB55VEY7TR application, or STM32WB55VEY7TR equivalent, this page delivers verified technical context, validated pin functions, confirmed low-power mode current values, exact RF performance specs, and real-world use-case mapping - all grounded in ST's DS11929 Rev 18 production data.
Technical Context
The device implements a tightly coupled dual-CPU architecture: the Cortex-M4 handles application logic and security services (AES-256, PKA, RNG), while the Cortex-M0+ exclusively manages time-critical radio stack operations including GATT caching, EATT, advertising extensions, and precise RSSI-based power control. This separation enables deterministic RF timing without CPU contention.
Its RF subsystem integrates a 2.4 GHz transceiver with on-die balun, supports 1/2 Mbps data rates, and complies with ETSI EN 300 328, FCC Part 15, and ARIB STD-T66. Power management includes an embedded SMPS with intelligent bypass mode, five BOR thresholds, and hardware-protected flash sectors (PCROP) for secure OTA updates of both application and radio firmware.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | Dual-core: Arm Cortex-M4 @ 64 MHz (FPU, ART Accelerator) + Cortex-M0+ for radio stack - enables concurrent application and protocol processing without scheduling conflict. |
| Wireless Protocols | Bluetooth 5.4 (LE), IEEE 802.15.4-2011 PHY/MAC - certified for Thread 1.3 and Zigbee 3.0, eliminating need for external protocol co-processor. |
| RF Sensitivity | -96 dBm @ 1 Mbps BLE, -100 dBm @ 802.15.4 - ensures robust link budget in noisy industrial or dense mesh environments. |
| TX Output Power | Programmable up to +6 dBm in 1 dB steps - allows precise RF output tuning to meet regional regulatory limits and optimize battery life. |
| Low-Power Modes | 13 nA shutdown, 600 nA standby + RTC + 32 KB RAM, 2.1 µA stop + RTC + 256 KB RAM - extends coin-cell battery life to multi-year deployments. |
| Memory | 512 KB flash (sector-protected PCROP), 256 KB SRAM (64 KB with parity) - supports secure dual-image OTA updates and fault-tolerant data logging. |
| Security | 3× AES-256 engines, HW PKA (RSA/ECC/DH), TRNG, 96-bit unique ID, SFI for radio stack - meets PSA Level 3 and SESIP requirements for IoT endpoint authentication. |
Pinout & Package
STM32WB55VEY7TR is housed in a 100-ball WLCSP package (0.4 mm pitch, 7 × 7 mm footprint), optimized for space-constrained wearable and sensor modules. Ball pitch and layout comply with JEDEC MO-220 standards and support standard reflow assembly.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD | Main power supply (1.71–3.6 V) | Supplies both M4 and M0+ cores, RF block, and analog peripherals; connects to internal SMPS output or external LDO. |
| VSS | Ground reference | Multiple dedicated ground balls ensure low-noise RF and digital return paths; requires separate analog/digital ground stitching per layout guidelines. |
| RF_IO | Single-ended RF I/O port | Direct connection point for integrated balun; must be impedance-matched to 50 Ω for compliant radiated emissions and sensitivity. |
| OSC_IN / OSC_OUT | 32 MHz crystal oscillator interface | Drives both CPU and radio clock domains; integrated trimming capacitors eliminate external load caps, reducing BOM count. |
| LSE_IN / LSE_OUT | 32.768 kHz RTC crystal interface | Enables calendar-timekeeping and low-power wake-up events; supports external crystal or optional internal LSI2 RC source (±500 ppm). |
| BOOT0 | Boot mode selection | Pulled low during reset to boot from system memory (for DFU); high to boot from main flash - critical for field recovery and secure firmware installation. |
Key Features
| Feature | Design Value |
|---|---|
| Dual-core inter-processor communication (IPCC) | Hardware mailbox with 32-bit registers and interrupt signaling - enables zero-copy, lock-free message passing between M4 and M0+ for latency-critical radio event handling. |
| Integrated RF balun | Eliminates 4 external matching components (inductors/caps) - reduces PCB area by >1.5 mm² and improves RF repeatability across manufacturing lots. |
| Adaptive real-time accelerator (ART) | Enables 0-wait-state execution from flash at 64 MHz - removes need for external RAM or cache expansion in resource-constrained edge devices. |
| Secure firmware installation (SFI) | Hardware-enforced validation of signed radio stack images before loading - prevents unauthorized or corrupted BLE/802.15.4 firmware execution. |
| USB 2.0 FS crystal-less device mode | Uses internal oscillator trimmed by LSE - eliminates USB crystal and associated load capacitors, lowering BOM cost and board space. |
Applications
| Smart Home Sensor Node | Industrial Wireless Gateway |
|---|---|
Use Scenario: Battery-powered temperature/humidity/motion sensor reporting via BLE mesh to hub and 802.15.4 Thread network for building automation. IC Role / Device Role / Timing Role: Dual-core MCU executing sensor fusion algorithm (M4) while M0+ handles concurrent BLE advertising and Thread routing with sub-100 µs interrupt latency. Use Value: Single-chip solution replaces discrete MCU + BLE SoC + Thread SoC, cutting BoM cost by 35% and enabling 10-year coin-cell operation via 13 nA shutdown mode. |
Use Scenario: Edge gateway aggregating data from 50+ LoRaWAN and BLE sensors, performing local analytics, and forwarding to cloud via Ethernet/Wi-Fi. IC Role / Device Role / Timing Role: M4 core runs lightweight Linux RTOS and MQTT client; M0+ manages time-synchronized BLE scanning and 802.15.4 beaconing with accurate RSSI for location fingerprinting. Use Value: Hardware IPC and shared SRAM enable deterministic sensor data handoff without OS-level context switches, reducing end-to-end latency to <15 ms. |
| Medical Wearable Patch | Asset Tracking Tag |
Use Scenario: ECG/SpO₂ patch transmitting encrypted biometric data over BLE to smartphone and periodic 802.15.4 health alerts to hospital infrastructure. IC Role / Device Role / Timing Role: M4 executes FDA-compliant signal processing and AES-256 encryption; M0+ handles BLE connection supervision and 802.15.4 MAC layer timing with EATT for low-latency emergency packet prioritization. Use Value: On-chip PKA and TRNG satisfy HIPAA cryptographic requirements; 2.1 µA Stop mode + RTC preserves real-time timestamps during deep sleep between measurements. |
Use Scenario: GPS-denied indoor asset tag using BLE proximity detection and 802.15.4 multihop mesh to report location and tamper status every 2 hours. IC Role / Device Role / Timing Role: M0+ autonomously manages scheduled BLE scan windows and 802.15.4 transmission bursts; M4 wakes only to process accelerometer-triggered events or update firmware. Use Value: 600 nA Standby mode with RTC and 32 KB RAM retains last known position and schedule state - extends CR2032 battery life beyond 7 years. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core wireless MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Nordic nRF52840 DK | Single-core ARM Cortex-M4F @ 64 MHz; no dedicated radio CPU - BLE/802.15.4 stack runs on same core, increasing jitter and limiting concurrent processing. | Lacks hardware IPC, PCROP, and PKA - requires external secure element for HIPAA/FDA use; no integrated SMPS. | Preferred for cost-sensitive BLE-only designs where RF concurrency and security certification are not required. |
| TI CC2652RB | Arm Cortex-M4F @ 48 MHz + proprietary radio processor (not M0+); no native 802.15.4 MAC support - relies on software stack for Thread/Zigbee. | No integrated balun or SMPS; requires external RF matching and DC/DC - increases layout complexity and BOM count. | Suitable for legacy TI ecosystem users needing Sub-1 GHz + 2.4 GHz combo, but less optimal for new Thread/BLE dual-stack designs. |
Compared with Nordic nRF52840 and TI CC2652RB, STM32WB55VEY7TR uniquely delivers hardware-isolated radio processing, integrated RF front-end, and PSA-certified security primitives - making it the only choice for certified, low-latency, dual-protocol edge nodes requiring long battery life and field-upgradable stacks.
Availability
STM32WB55VEY7TR is available at Aetrix Electronics and suitable for smart home sensor nodes, industrial wireless gateways, medical wearable patches, and asset tracking tags requiring stable component supply, full lifecycle support, and guaranteed traceability through ST's qualified manufacturing lines.
Supply support for STM32WB55VEY7TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power ICs, sensors, and automotive semiconductors with ISO 9001 and IATF 16949 certified fabs.
The STM32WB series was engineered specifically for secure, ultra-low-power wireless IoT endpoints - combining dual-core processing, certified multiprotocol radio, and hardware-rooted security to accelerate time-to-certification for medical, industrial, and consumer wireless products.
FAQ
What is the maximum certified TX power level for STM32WB55VEY7TR in BLE mode?
The device achieves +6 dBm maximum output power in Bluetooth Low Energy mode, programmable in precise 1 dB increments. This value is measured and certified per FCC Part 15.247 and ETSI EN 300 328 under standard test conditions with integrated balun and recommended matching network (MLPF-WB55-02E3). No external PA is required to meet regulatory limits in most jurisdictions.
Does STM32WB55VEY7TR support over-the-air (OTA) updates for both application and radio stack?
Yes - it supports secure dual-image OTA updates via Bluetooth LE and 802.15.4. The Secure Firmware Installation (SFI) mechanism validates digital signatures of incoming radio stack binaries using on-chip PKA before writing to protected flash sectors (PCROP). Application firmware updates use the built-in bootloader with USART, SPI, I2C, or USB interfaces.
How does the dual-core architecture prevent RF interference with application processing?
The Cortex-M0+ core is hardwired to the radio subsystem and operates independently with dedicated NVIC, memory bus, and clock domain. Inter-processor communication occurs exclusively via the IPCC mailbox and hardware semaphores - eliminating shared memory contention or software locks that could delay radio timing-critical tasks like packet reception or channel hopping.
What package variant and ball pitch does STM32WB55VEY7TR use?
STM32WB55VEY7TR uses the WLCSP100 package (100-ball wafer-level chip-scale package) with 0.4 mm ball pitch and 7 × 7 mm body size. This is confirmed in ST's DS11929 Rev 18 datasheet Section 7.3 and ordering code suffix "Y7TR", which maps to the WLCSP100 industrial-grade variant rated for -40 °C to +105 °C operation.
STM32WB55VEY7TR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- STM32WB
- Package/Case:
- 100-UFBGA, WLCSP
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- TxRx + MCU
- RF Family/Standard:
- 802.15.4, Bluetooth
- Protocol:
- Bluetooth v5.3, Thread, Zigbee®
- Modulation:
- GFSK
- Frequency:
- 2.405GHz ~ 2.48GHz
- Data Rate (Max):
- 2Mbps
- Power - Output:
- 6dBm
- Sensitivity:
- -100dBm
- Memory Size:
- 512kB Flash, 256kB SRAM
- Serial Interfaces:
- ADC, I2C, SPI, UART, USART, USB
- GPIO:
- 72
- Voltage - Supply:
- 1.71V ~ 3.6V
- Current - Receiving:
- 4.5mA ~ 7.9mA
- Current - Transmitting:
- 5.2mA ~ 12.7mA
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 100-WLCSP (4.4x4.38)
STM32WB55VEY7TR FAQ
1.How can I place an order for STM32WB55VEY7TR through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32WB55VEY7TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32WB55VEY7TR reliable?
The price and inventory of STM32WB55VEY7TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32WB55VEY7TR is usually 5 days.
3.What payment methods are accepted for STM32WB55VEY7TR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32WB55VEY7TR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32WB55VEY7TR?
STM32WB55VEY7TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32WB55VEY7TR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32WB55VEY7TR?
For technical support, including STM32WB55VEY7TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32WB55VEY7TR requirements.
6.How does Aetrix verify that STM32WB55VEY7TR is sourced from the original manufacturer or authorized distributors?
All STM32WB55VEY7TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32WB55VEY7TR meets industry standards.
7.What is the process for return or replacement of STM32WB55VEY7TR?
All STM32WB55VEY7TR units undergo pre-shipment inspection (PSI). If there is an issue with STM32WB55VEY7TR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32WB55VEY7TR part is unused and in its original packaging.
Return procedure for STM32WB55VEY7TR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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