STMicroelectronics STM32WL33CBV6TR
- Part No.:
- STM32WL33CBV6TR
- Manufacturer:
- STMicroelectronics
- Category:
- RF Transceiver ICs
- Package:
- 48-VFQFN Exposed Pad
- Datasheet:
-
STM32WL33CBV6TR.pdf
- Description:
- IC RF TXRX+MCU 802.15.4 48VFQFPN
- Quantity:
- Payment:

- Shipping:

Inventory:3,792
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
STM32WL33CBV6TR from STMicroelectronics is an ultra-low-power, multiprotocol sub-1 GHz wireless system-on-chip integrating an Arm® Cortex®-M0+ 32-bit MCU (64 MHz), 256-Kbyte flash, 32-Kbyte SRAM, and a fully configurable RF transceiver supporting 2(G)FSK/4(G)FSK/ASK/OOK/D-BPSK modulation across 159–958 MHz bands. It delivers +20 dBm TX power, -132 dBm RX sensitivity at 300 bit/s (433 MHz OOK), and operates from 1.7–3.6 V in -40°C to +105°C for battery-powered LPWAN edge nodes.
For engineers reviewing the STM32WL33CBV6TR datasheet, STM32WL33CBV6TR pinout, STM32WL33CBV6TR application, or STM32WL33CBV6TR equivalent, key selection criteria include certified sub-GHz radio compliance (ETSI EN 300 220, FCC Part 15/90), autonomous wakeup receiver (LPAWUR, -54 dBm, 4 µA), integrated SMPS with dynamic bypass, and hardware AES-128/TRNG security for secure over-the-air updates in asset tracking and smart metering systems.
Technical Context
The STM32WL33CBV6TR implements a tightly coupled dual-domain architecture: the Cortex-M0+ core manages application logic and protocol stacks while the dedicated RF subsystem handles autonomous radio sequencing (sniff mode, frequency hopping, listen-before-talk) via hardware state machine. Its RF front-end uses low-IF RX and direct-modulation TX with programmable PA topologies (TX/TXHP modes) and AGC-driven interferer rejection.
Power management integrates a digitally controlled SMPS (1.2–2.4 V output), static/dynamic bypass-on-the-fly (BOF), and three ultra-low-power states: Shutdown (14 nA), Deepstop (960 nA), and WFI (1.3 mA). The LPAWUR operates independently on 32 kHz clock (LSI or LSE) with Manchester-encoded OOK frame detection (40-bit sync + 8-bit 0x99 sync + 56-bit payload + 16-bit CRC).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm® Cortex®-M0+, 64 MHz max - enables real-time protocol stack execution with <1 µs interrupt latency for time-critical LPWAN packet handling. |
| Memory | 256-Kbyte flash / 32-Kbyte SRAM (dual-bank) / 1-Kbyte OTP - supports secure bootloader storage, firmware OTA updates, and retained context across Deepstop wakeups. |
| RF Frequency Bands | 159–185 MHz / 413–479 MHz / 826–958 MHz - covers global ISM/SRD bands including 433 MHz (EU), 868 MHz (EU), and 915 MHz (US) without external filter reconfiguration. |
| TX Power & RX Sensitivity | +20 dBm max TX (TX+TXHP) / -132 dBm @300 bit/s (433 MHz OOK) - achieves >10 km range in rural LoRa-like deployments with single-chip integration. |
| Modulation Support | 2(G)FSK, 4(G)FSK, OOK, ASK, D-BPSK, DSSS - enables native compatibility with W-MBUS, Sigfox, MiOTY, KNX-RF, and IEEE 802.15.4g without external RFIC. |
| Ultra-Low-Power Modes | 14 nA Shutdown / 960 nA Deepstop / 4 µA LPAWUR always-on - extends 10-year battery life in sealed utility meters using periodic wake-up polling. |
| Security | AES-128 co-processor + 16-bit TRNG + SWD disable + read-out protection - meets IEC 62443-3-3 SL2 requirements for encrypted sensor data transmission. |
Pinout & Package
VFQFPN48 package (6 × 6 mm, 0.4 mm pitch), RoHS-compliant ECOPACK2, with 32 GPIOs (all retention-capable), 3 analog inputs for ADC, and dedicated RF matching pins (ANT, VDDRF, VSSRF) routed to exposed thermal pad.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD, VSS | Digital power supply and ground | Core logic domain (1.7–3.6 V); requires local 100 nF decoupling per VDD pin for stable 64 MHz operation. |
| VDDRF, VSSRF | RF power supply and ground | Isolated analog rail for transceiver; must be filtered separately from digital VDD to prevent RX desensitization. |
| ANT | RF antenna interface | Single-ended 50 Ω port; requires external matching network (L/C) tuned to target band (e.g., 868 MHz) for +20 dBm output. |
| PA10 / PB14 | TX_SEQUENCE (AF2) | Open-drain signal active high during TX - used to control external TX/RX antenna switch or PA enable timing. |
| PA8 / PA11 | RX_SEQUENCE (AF2) | Open-drain signal active high during RX - synchronizes external LNA bias or interference mitigation circuitry. |
| OSC_IN / OSC_OUT | HSE crystal oscillator | 48 MHz fundamental-mode crystal (±10 ppm) with internal trimming capacitors - eliminates external load caps for BOM reduction. |
| LSE_IN / LSE_OUT | LSE crystal oscillator | 32.768 kHz crystal for RTC and LPAWUR timing - enables precise 1 kbit/s Manchester frame detection during Deepstop. |
Key Features
| Feature | Design Value |
|---|---|
| Fully autonomous RF sequencer | Hardware state machine executes sniff mode, frequency hopping, and LBT without CPU intervention - reduces active time by >95% in duty-cycled sensor networks. |
| Integrated SMPS with BOF | Configurable 1.2–2.4 V output + static/dynamic bypass - improves RX sensitivity by 3 dB when disabling SMPS noise during reception. |
| LPAWUR with Manchester OOK | 4 µA always-on receiver detecting 0x99-sync frames - wakes full SoC from Deepstop in <50 µs, enabling sub-second response to urgent alarms. |
| Hardware crypto acceleration | AES-128 engine + TRNG completes 128-bit encryption in <100 cycles - secures firmware updates without impacting real-time sensor sampling at 1 MSPS. |
| Multi-protocol RF support | Single register-set configuration for W-MBUS Mode N/S, Sigfox uplink, and MiOTY burst - eliminates need for external protocol translators in multi-standard gateways. |
Applications
| Asset Tracking | Wireless Sensors |
|---|---|
Use Scenario: GPS-denied indoor/outdoor cargo monitoring with periodic location reporting via private LPWAN. IC Role / Device Role / Timing Role: Standalone wireless node executing proprietary geofence-aware protocol stack and managing GNSS assist-data caching. Use Value: 10-year battery life achieved via Deepstop + LPAWUR-triggered wakeups and +20 dBm TX for reliable gateway link budget in metal-rich warehouses. | Use Scenario: Battery-powered temperature/humidity sensors deployed in HVAC ducts with 15-minute reporting intervals. IC Role / Device Role / Timing Role: Integrated sensing hub performing ADC sampling, CRC validation, and adaptive air-rate selection (300 kbit/s → 10 kbit/s) based on RSSI. Use Value: Sub-1 µA average current enabled by SMPS dynamic bypass during RX and hardware sequencer-managed low-duty-cycle transmissions. |
| Smart Metering | Building Automation |
Use Scenario: Water/gas heat cost allocators transmitting consumption data hourly to concentrators using W-MBUS Mode S. IC Role / Device Role / Timing Role: Certified W-MBUS endpoint with hardware AES encryption of billing data and tamper-detection GPIO monitoring. Use Value: ETSI EN 13757-4 compliance met natively; no external RFIC or crypto IC required - reduces BOM cost by 32% vs discrete solutions. | Use Scenario: Wireless occupancy/lighting controllers in office spaces using KNX-RF protocol with bidirectional command/response. IC Role / Device Role / Timing Role: Dual-role node acting as both KNX-RF sensor (motion detection) and actuator (relay control) with deterministic 100 ms latency. Use Value: Hardware timer-synchronized RX windows and I/Q data access allow custom KNX-RF waveform tuning for coexistence with Wi-Fi/BLE in dense RF environments. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar sub-GHz wireless MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SX1262 + STM32L4 | Discrete RFIC + separate ultra-low-power MCU - requires external SPI interface, clock routing, and RF matching per band. | Lacks integrated LPAWUR and hardware sequencer; demands custom driver development for W-MBUS/Sigfox. | Select when legacy design reuse or multi-band flexibility (e.g., simultaneous 433/868 MHz) outweighs BOM simplification. |
| CC1312R | Arm Cortex-M4F + proprietary RF core - no native 4(G)FSK or DSSS; limited to TI's SimpleLink stack and proprietary protocols. | Requires TI-certified gateway infrastructure; incompatible with ETSI EN 300 220 category 1 self-certification path. | Select only for brownfield TI ecosystem deployments where migration to open standards is not required. |
Compared with SX1262+STM32L4 and CC1312R, the STM32WL33CBV6TR provides single-chip regulatory certification, hardware-accelerated multi-protocol support, and autonomous LPAWUR - reducing time-to-certification by 6 months and eliminating inter-IC timing skew in critical LPWAN timing budgets.
Availability
STM32WL33CBV6TR is available at Aetrix Electronics and suitable for asset tracking, smart metering, and industrial wireless sensor networks requiring stable component supply across automotive-grade temperature ranges (-40°C to +105°C) and long-lifecycle commitments.
Supply support for STM32WL33CBV6TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, MEMS, and RF solutions for industrial, automotive, and consumer markets.
The STM32WL33xx product line targets certified LPWAN endpoints, integrating sub-GHz radio, ultra-low-power MCU, and security accelerators into a single die to eliminate RF design complexity and accelerate time-to-market for battery-operated IoT devices.
FAQ
What is the maximum certified TX power level for STM32WL33CBV6TR in ETSI EN 300 220 Category 1 applications?
The STM32WL33CBV6TR achieves +14 dBm certified output power in 868 MHz band under ETSI EN 300 220 Category 1, verified with integrated PA and standard reference antenna. Higher +20 dBm operation requires external filtering and additional certification testing per national authority requirements.
Does STM32WL33CBV6TR support hardware-based W-MBUS Mode N and Mode S simultaneously?
No - W-MBUS Mode N (uplink-only) and Mode S (bidirectional) require distinct RF parameter configurations (air rate, preamble length, sync word). The device supports either mode via software register reconfiguration, but not concurrent dual-mode operation due to shared RF state machine resources.
How does the LPAWUR interact with the main RF transceiver during Deepstop wake-up?
Upon detecting a valid Manchester OOK frame, LPAWUR asserts a dedicated wakeup interrupt that exits Deepstop within 50 µs. The main RF transceiver remains powered off until firmware explicitly initializes it - ensuring zero current draw from RF circuitry until post-wakeup application logic determines transmission necessity.
Can the SMPS be disabled while retaining full 64 MHz CPU performance?
Yes - SMPS can be disabled via static bypass-on-the-fly (BOF) mode, connecting VFBSD directly to VDD. This maintains 64 MHz operation using the main LDO, though peak TX power is limited to +14 dBm and RX sensitivity degrades by ~1.5 dB due to LDO noise coupling.
STM32WL33CBV6TR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 48-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- -
- Type:
- TxRx + MCU
- RF Family/Standard:
- 802.15.4
- Protocol:
- KNX, LPWAN, Sigfox, Zigbee®
- Modulation:
- 2-FSK, 2-GFSK, 4-FSK, 4-GFSK, ASK, DBPSK, DSSS, OOK
- Frequency:
- 413MHz ~ 479MHz, 826MHz ~ 958MHz
- Data Rate (Max):
- 600kbps
- Power - Output:
- 20dBm
- Sensitivity:
- -132dBm
- Memory Size:
- 256kB Flash, 32kB SRAM
- Serial Interfaces:
- GPIO, I2C, I2S, IrDA, JTAG, PCM, PWM, SPI, UART, USART
- GPIO:
- 32
- Voltage - Supply:
- 1.7V ~ 3.6V
- Current - Receiving:
- 4mA
- Current - Transmitting:
- 10mA ~ 80mA
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 48-VFQFPN (6x6)
STM32WL33CBV6TR FAQ
1.How can I place an order for STM32WL33CBV6TR through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32WL33CBV6TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32WL33CBV6TR reliable?
The price and inventory of STM32WL33CBV6TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32WL33CBV6TR is usually 5 days.
3.What payment methods are accepted for STM32WL33CBV6TR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32WL33CBV6TR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32WL33CBV6TR?
STM32WL33CBV6TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32WL33CBV6TR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32WL33CBV6TR?
For technical support, including STM32WL33CBV6TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32WL33CBV6TR requirements.
6.How does Aetrix verify that STM32WL33CBV6TR is sourced from the original manufacturer or authorized distributors?
All STM32WL33CBV6TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32WL33CBV6TR meets industry standards.
7.What is the process for return or replacement of STM32WL33CBV6TR?
All STM32WL33CBV6TR units undergo pre-shipment inspection (PSI). If there is an issue with STM32WL33CBV6TR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32WL33CBV6TR part is unused and in its original packaging.
Return procedure for STM32WL33CBV6TR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
STM32WL33CBV6TR Tags

-
ESP32-D0WD-V3
Espressif Systems

-
ESP8266EX
Espressif Systems

-
ESP32-S3
Espressif Systems

-
NRF24L01P-R7
Nordic Semiconductor ASA

-
NRF24L01P-R
Nordic Semiconductor ASA

-
ESP32-U4WDH
Espressif Systems

-
DA14531-00000OG2
Renesas

-
ESP32-C6FH4
Espressif Systems

-
DA14531-00000FX2
Renesas

-
NRF24L01P-T
Nordic Semiconductor ASA

-
NRF52810-QCAA-R
Nordic Semiconductor ASA

-
ESP32-S3FN8
Espressif Systems
Tech Hub
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
