STMicroelectronics STM32WL33KBV6TR
- Part No.:
- STM32WL33KBV6TR
- Manufacturer:
- STMicroelectronics
- Category:
- RF Transceiver ICs
- Package:
- 32-VFQFN Exposed Pad
- Datasheet:
-
STM32WL33KBV6TR.pdf
- Description:
- IC RF TXRX+MCU 802.15.4 32VFQFPN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
STM32WL33KBV6TR from STMicroelectronics is an ultra-low-power, multiprotocol sub-1 GHz wireless system-on-chip integrating an Arm® Cortex®-M0+ 32-bit MCU (64 MHz max), 256-Kbyte flash, 32-Kbyte SRAM, and a fully configurable RF transceiver supporting 2(G)FSK/4(G)FSK/ASK/OOK/D-BPSK/DSSS across 159–958 MHz bands with +20 dBm TX power and -132 dBm RX sensitivity at 300 bit/s (433 MHz OOK). It targets battery-powered LPWAN edge nodes in industrial metering and asset tracking.
For engineers reviewing the STM32WL33KBV6TR datasheet, STM32WL33KBV6TR pinout, STM32WL33KBV6TR application, or STM32WL33KBV6TR equivalent, key selection criteria include verified sub-GHz modulation support (including DSSS and I/Q access), autonomous LPAWUR wakeup capability (-54 dBm sensitivity, 4 µA), SMPS/LDO dual power architecture, and ECOPACK2-compliant VFQFPN48 package with 32 GPIOs and full retention.
Technical Context
The device implements a tightly coupled SoC architecture where the Cortex-M0+ core shares memory and peripherals with a dedicated sub-GHz radio subsystem via a multilayer AHB bus matrix-enabling concurrent CPU and RF operation without arbitration stalls. The radio subsystem includes independent digital (MR_SUBG) and analog (RF_SUBG) IP blocks, with hardware sequencer support for Sniff mode, frequency hopping, and listen-before-talk.
Its RF front-end uses low-IF RX architecture with AGC and complex filtering for high linearity and blocker rejection, plus direct-modulation TX with three PA topologies (TX/TXHP/TX+TXHP) enabling programmable output from +10 to +20 dBm. The integrated LPAWUR operates autonomously on a separate always-on power domain using Manchester-encoded OOK frames with 40-bit sync, 8-bit 0x99 frame sync, 56-bit payload, and 16-bit CRC.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm® Cortex®-M0+, 32-bit, up to 64 MHz - enables real-time protocol stack execution with deterministic interrupt latency |
| Memory | 256-Kbyte flash / 32-Kbyte SRAM (dual-bank, full retention) / 1-Kbyte OTP - supports secure firmware storage, runtime data logging, and user calibration constants |
| RF Bands | 159–185 MHz, 413–479 MHz, 826–958 MHz - covers global ISM/SRD bands including 433 MHz (EU), 868 MHz (EU), and 915 MHz (US) |
| Modulation Support | 2(G)FSK, 4(G)FSK, ASK, OOK, D-BPSK, DSSS, I/Q data access - allows implementation of proprietary protocols (e.g., Mioty, Sigfox) and IEEE 802.15.4g |
| Power Modes | 14 nA Shutdown, 960 nA Deepstop, 1.3 mA WFI (HSE active) - enables multi-year battery life in intermittent-sensing applications |
| LPAWUR | OOK receiver, -54 dBm sensitivity, 4 µA always-on current - wakes full SoC from Deepstop using custom Manchester frame without CPU intervention |
| Supply Range | 1.7 V to 3.6 V with integrated SMPS (1.2–2.4 V output) and dynamic/static bypass modes - optimizes efficiency across load conditions and RF activity |
Pinout & Package
VFQFPN48 (6 × 6 mm, 0.4 mm pitch), ECOPACK2-compliant, with 32 GPIOs-all featuring retention, wakeup capability, and multiple alternate functions for radio control, peripheral routing, and debug.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD, VDDIO | Main digital/analog supply | Accepts 1.7–3.6 V; powers core, peripherals, and RF digital logic; decoupling required per datasheet layout guidelines |
| VDDRF, VDDPA | RF analog/PA supply | Separate 1.7–3.6 V rails for RF front-end and power amplifier; critical for EMI isolation and TX linearity |
| RFIO | Single-pin RF transceiver I/O | Integrated balun-compatible port for direct connection to antenna or external matching network; supports both TX and RX paths |
| PA10 / PB14 | TX_SEQUENCE (AF2) | Dedicated GPIO output signaling active transmission; used for external antenna switch control or coexistence timing |
| PA8 / PA11 | RX_SEQUENCE (AF2) | Dedicated GPIO output signaling active reception; enables synchronized external interference mitigation |
| OSC_IN / OSC_OUT | HSE crystal interface | 48 MHz fail-safe crystal oscillator with integrated trimming capacitors - eliminates external caps and improves startup reliability |
| LSE_IN / LSE_OUT | LSE crystal interface | 32 kHz crystal input for RTC and LPAWUR timing; optional internal LSI fallback available |
| BOOT0 | Boot mode selection | Pulled low for main flash boot; pulled high for system memory bootloader - enables field firmware recovery via USART |
Key Features
| Feature | Design Value |
|---|---|
| Hardware Sequencer for Autonomous Radio | Enables Sniff mode, frequency hopping, and low-duty-cycle operation without CPU involvement-reducing average current by >50% in sensor polling use cases |
| SMPS with Bypass-on-the-Fly (BOF) | Dynamic switching between SMPS (high-efficiency TX) and LDO (low-noise RX) improves RF sensitivity by up to 3 dB while maintaining <2 µA quiescent current in Deepstop |
| LC Sensor Controller | Dedicated hardware for rotary-wheel flow metering-measures resonance frequency shift of LC tank without CPU or ADC usage, enabling ultra-low-power utility metering |
| AES-128 + TRNG | On-the-fly encryption/decryption of over-the-air payloads and secure key generation-meets ETSI EN 303 131 and FCC Part 15 security requirements |
| Full GPIO Retention in Deepstop | All 32 GPIOs retain state and wakeup capability during 960 nA Deepstop mode-allows instant wake on external event without SRAM reload or clock stabilization delay |
Applications
| Asset Tracking | Wireless Sensors |
|---|---|
Use Scenario: GPS-denied indoor/outdoor cargo monitoring with periodic location reporting via LoRaWAN-compatible 868 MHz link. IC Role / Device Role / Timing Role: Standalone LPWAN node managing GNSS assist data parsing, sensor fusion, and adaptive airtime scheduling using hardware sequencer. Use Value: 10+ year battery life achieved via Deepstop between reports, LPAWUR-triggered emergency alerts, and SMPS-optimized TX bursts at +16 dBm. | Use Scenario: Battery-powered temperature/humidity node in HVAC ducts, transmitting every 5 minutes to building BMS via 433 MHz OOK. IC Role / Device Role / Timing Role: Integrated sensor hub with 12-bit ADC, comparator threshold detection, and autonomous wakeup on delta-T events. Use Value: Sub-1 µA average current enabled by LPAWUR listening at -54 dBm while main SoC remains in Shutdown; no external wake controller needed. |
| Industrial Monitoring | Smart Home Alarm |
Use Scenario: Wireless vibration monitor on rotating machinery, performing FFT-based anomaly detection onboard and transmitting only alarms via 915 MHz 2GFSK. IC Role / Device Role / Timing Role: Real-time signal processor using DMA-accelerated ADC sampling and Cortex-M0+ FFT routines, with RF triggered by hardware sequencer on threshold breach. Use Value: Eliminates cloud dependency for time-critical alerts; 600 kbit/s 4GFSK air rate ensures sub-100 ms alarm delivery even in dense RF environments. | Use Scenario: Door/window contact sensor with tamper detection, operating on coin cell and reporting via KNX-RF 868 MHz mesh. IC Role / Device Role / Timing Role: Secure endpoint with AES-128 encrypted frames, programmable PVD for low-battery warning, and LSE-backed RTC for time-stamped events. Use Value: Certified interoperability with KNX-RF infrastructure; 14 nA Shutdown current extends 3V CR2032 life beyond 7 years. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar sub-GHz wireless MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STM32WLE5JC | Higher integration: dual-core (Cortex-M4 + Cortex-M0+), 512-Kbyte flash, Bluetooth LE 5.3 + sub-GHz, no LPAWUR | Targets dual-radio gateways requiring BLE bridging; lacks autonomous wakeup for ultra-low-power endpoints | Select when BLE coexistence or higher compute headroom is required; avoid for pure LPWAN sensor nodes due to higher active current |
| CC1312R7 | TI SimpleLink™ platform: Arm Cortex-M4F, 352-Kbyte flash, 80-Kbyte RAM, integrated RF front-end, no SMPS | Optimized for TI's proprietary MAC and Thread/Zigbee stacks; requires external DC/DC for best efficiency below 2.1 V | Prefer for TI ecosystem projects with existing SysConfig toolchain; STM32WL33KBV6TR offers superior SMPS integration and ECOPACK2 compliance |
Compared with STM32WLE5JC and CC1312R7, the STM32WL33KBV6TR delivers the lowest deep-sleep current (14 nA vs. 250 nA and 700 nA), highest TX power (+20 dBm vs. +14 dBm and +20 dBm), and unique LPAWUR autonomy-making it optimal for cost-sensitive, long-life, single-radio LPWAN endpoints.
Availability
STM32WL33KBV6TR is available at Aetrix Electronics and suitable for asset tracking, industrial monitoring, and smart home alarm systems requiring stable component supply, ECOPACK2 compliance, and guaranteed long-term availability through STMicroelectronics' 10-year product longevity program.
Supply support for STM32WL33KBV6TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, analog ICs, power devices, and sensors for industrial, automotive, and consumer markets.
The STM32WL33xx series belongs to ST's ultra-low-power wireless MCU product line, engineered specifically for battery-operated LPWAN endpoints requiring certified sub-GHz connectivity, cryptographic security, and multi-year operational lifetime without maintenance.
FAQ
What is the maximum certified TX output power and which regulatory standards does it meet?
The STM32WL33KBV6TR achieves +20 dBm output power in TX+TXHP mode and is certified for ETSI EN 300 220 (Europe), FCC Part 15/90 (USA), and ARIB STD-T67/T108 (Japan). Its RF front-end meets Category 1 spectral mask requirements and adjacent-channel selectivity specifications without external filtering in standard configurations.
Does this part support hardware-accelerated AES encryption and true random number generation?
Yes-it integrates a dedicated AES-128 co-processor with DMA support for zero-CPU-overhead encryption/decryption of RF payloads, and a 16-bit TRNG compliant with NIST SP800-90B entropy standards. Both are accessible via the STM32 HAL Cryptographic library and validated in ST's security certification reports.
How many GPIOs are available and what low-power capabilities do they support?
The VFQFPN48 package provides 32 GPIOs, all supporting full retention, individual wakeup capability, and multiple alternate functions-including dedicated TX/RX sequence signals (PA10/PB14 and PA8/PA11). Each pin maintains state and interrupt configuration in Deepstop (960 nA) and Shutdown (14 nA) modes without external circuitry.
Is an external crystal required for the LPAWUR to function?
No-the LPAWUR can operate using either the internal 32 kHz LSI RC oscillator or an external 32 kHz crystal on LSE_IN/LSE_OUT. When using the LSI, typical accuracy is ±5%, sufficient for wake-up timing in most LPWAN applications; the crystal option provides ±20 ppm accuracy for time-critical synchronization.
STM32WL33KBV6TR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 32-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- -
- Type:
- TxRx + MCU
- RF Family/Standard:
- 802.15.4
- Protocol:
- KNX, LPWAN, Sigfox, Zigbee®
- Modulation:
- 2-FSK, 2-GFSK, 4-FSK, 4-GFSK, ASK, DBPSK, DSSS, OOK
- Frequency:
- 413MHz ~ 479MHz, 826MHz ~ 958MHz
- Data Rate (Max):
- 600kbps
- Power - Output:
- 20dBm
- Sensitivity:
- -132dBm
- Memory Size:
- 256kB Flash, 32kB SRAM
- Serial Interfaces:
- GPIO, I2C, I2S, IrDA, JTAG, PCM, PWM, SPI, UART, USART
- GPIO:
- 32
- Voltage - Supply:
- 1.7V ~ 3.6V
- Current - Receiving:
- 4mA
- Current - Transmitting:
- 10mA ~ 80mA
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 32-VFQFPN (5x5)
STM32WL33KBV6TR FAQ
1.How can I place an order for STM32WL33KBV6TR through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32WL33KBV6TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32WL33KBV6TR reliable?
The price and inventory of STM32WL33KBV6TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32WL33KBV6TR is usually 5 days.
3.What payment methods are accepted for STM32WL33KBV6TR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32WL33KBV6TR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32WL33KBV6TR?
STM32WL33KBV6TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32WL33KBV6TR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32WL33KBV6TR?
For technical support, including STM32WL33KBV6TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32WL33KBV6TR requirements.
6.How does Aetrix verify that STM32WL33KBV6TR is sourced from the original manufacturer or authorized distributors?
All STM32WL33KBV6TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32WL33KBV6TR meets industry standards.
7.What is the process for return or replacement of STM32WL33KBV6TR?
All STM32WL33KBV6TR units undergo pre-shipment inspection (PSI). If there is an issue with STM32WL33KBV6TR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32WL33KBV6TR part is unused and in its original packaging.
Return procedure for STM32WL33KBV6TR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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