STMicroelectronics STM32WL55JCI6

Overview

STM32WL55JCI6 from STMicroelectronics is a dual-core 32-bit Arm® Cortex®-M4/M0+ SoC integrating sub-GHz radio (LoRa®, (G)FSK, (G)MSK, BPSK), 256 KB flash, 64 KB SRAM, hardware AES-256 and PKA, operating from 1.8–3.6 V across –40 °C to +105 °C. It enables secure, ultra-low-power LPWAN node design for battery-operated sensor networks requiring long-range wireless telemetry.

For engineers reviewing the STM32WL55JCI6 datasheet, STM32WL55JCI6 pinout, STM32WL55JCI6 application, or STM32WL55JCI6 equivalent, key selection criteria include dual-core real-time partitioning, integrated RF transceiver performance (–148 dBm LoRa® RX sensitivity, +22 dBm TX), sub-GHz regulatory compliance (ETSI EN 300 220, FCC Part 15), and hardware security services (PCROP, SFU, RNG).

Technical Context

The device implements tightly coupled dual-CPU architecture: Cortex-M4 (48 MHz, ART Accelerator, DSP/MPU) handles application and protocol stack execution, while Cortex-M0+ (48 MHz, MPU) manages radio control and low-power state coordination via IPCC and HSEM. Radio subsystem includes fully integrated RF front-end with programmable TX output (up to +22 dBm) and high-sensitivity RX (–148 dBm @ LoRa® SF12), supporting multiple modulation schemes in 150–960 MHz band.

Power management integrates SMPS step-down converter, smart SMPS-to-LDO switch, and five low-power modes - including Shutdown (31 nA), Standby+RTC (360 nA), and Stop2+RTC (1.07 µA) - enabling multi-year battery life in remote sensing nodes. Security is enforced at silicon level via PCROP, RDP, WRP, AES-256, PKA, and secure bootloader with OTA update capability.

Key Specifications

Pinout & Package

STM32WL55JCI6 uses UFBGA73 (5 × 5 mm, 0.4 mm pitch) package with 73-ball layout optimized for RF integrity and compact LPWAN module integration. Pin assignment validated per DS13293 Rev 5 Section 4 (Pinouts, pin description and alternate functions).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar sub-GHz LPWAN SoC applications.

Compared with STM32WL55JCI6, STM32WL54JCI6 offers identical RF performance and security features at lower memory cost, while ASR-6501 lacks hardware-accelerated crypto and dual-core determinism - making it unsuitable for certified industrial or utility-grade deployments requiring secure over-the-air updates and strict timing isolation.

Availability

STM32WL55JCI6 is available at Aetrix Electronics and suitable for smart utility metering, industrial predictive maintenance, environmental monitoring, and agricultural telemetry requiring stable component supply across multi-year production cycles.

Supply support for STM32WL55JCI6 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, analog ICs, power devices, and MEMS sensors for industrial, automotive, and IoT markets.

The STM32WL series is ST's purpose-built LPWAN SoC product line targeting secure, battery-operated sub-GHz wireless nodes - combining Arm dual-core compute, certified radio, and hardware security in a single chip to accelerate LoRaWAN® and private protocol development.

FAQ

What RF certifications does STM32WL55JCI6 support out-of-the-box?

STM32WL55JCI6 is pre-certified for ETSI EN 300 220 (Europe), EN 300 113 (legacy), EN 301 166 (SRD), FCC CFR 47 Parts 15/24/90 (USA), and ARIB STD-T30/T-67/T-108 (Japan). Certification applies to reference designs using ST's recommended IPDs (e.g., S2LP companion chips) and layout guidelines - full test reports are available under NDA from ST.

Does STM32WL55JCI6 require external RF components for basic LoRa® operation?

No. STM32WL55JCI6 integrates complete RF transceiver, PA, LNA, and T/R switch. Only an external matching network (typically 3–5 passive components) and antenna are required. ST provides validated IPD modules (e.g., SMPS-732-01) that consolidate balun, filter, and matching into one 2.0 × 1.6 mm package for rapid compliance.

How is dual-core security enforced between Cortex-M4 and Cortex-M0+?

Security is enforced via Global TrustZone Controller (GTZC), which partitions memory (flash/SRAM) and peripherals into secure/non-secure regions. The M0+ runs in secure world and controls access to RF registers and crypto engines; M4 accesses them only through defined secure gateways (TZIC), preventing privilege escalation or side-channel leakage.

Can STM32WL55JCI6 operate in FSK mode while maintaining LoRaWAN® compliance?

Yes. The integrated radio supports simultaneous LoRa® and (G)FSK modulation in the same frequency band. LoRaWAN® v1.0.4 permits FSK for Class B beacon synchronization and proprietary FSK protocols (e.g., W-MBus) can coexist using ST's multi-modem firmware stack - validated in AN5289 application note.