STMicroelectronics STM32WL5MOCH6STR
- Part No.:
- STM32WL5MOCH6STR
- Manufacturer:
- STMicroelectronics
- Category:
- RF Transceiver ICs
- Package:
- 92-LGA
- Datasheet:
-
STM32WL5MOCH6STR.pdf
- Description:
- IC RF TXRX+MCU ISM<1GHZ 92LGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
STM32WL5MOCH6STR from STMicroelectronics is a certified, multiprotocol LPWAN system-in-package (SiP) module integrating the STM32WL55JC dual-core Arm® Cortex®-M4/M0+ MCU with sub-GHz radio transceiver, 256 KB flash, 64 KB SRAM, and embedded 32 MHz TCXO + 32 kHz RTC crystals. It supports LoRa®, (G)FSK, (G)MSK, and BPSK modulation across 864–928 MHz bands and delivers –148 dBm LoRa Rx sensitivity and +22 dBm programmable Tx output power for long-range IoT sensor nodes.
For engineers reviewing the STM32WL5MOCH6STR datasheet, STM32WL5MOCH6STR pinout, STM32WL5MOCH6STR application, or STM32WL5MOCH6STR equivalent, key selection criteria include its LGA92 (10×10 mm) SiP integration, dual-core secure firmware execution, STSAFE-A110 footprint compatibility, FCC/ISED/ARIB regulatory compliance, and hardware-configurable high/low-power RF output paths.
Technical Context
The STM32WL5MOCH6STR implements a fully integrated sub-GHz RF front-end with on-module matching network, IPD filter, and antenna interface - eliminating external RF design expertise. Its dual-core architecture enables concurrent real-time protocol stack processing (M4) and low-power scheduling (M0+), with dedicated hardware accelerators for AES-256, PKA, and CRC.
Radio operation is managed via two independent PA paths: BIAS_HP/VR_PA/VDDPA support +22 dBm high-power transmission, while BIAS_LP enables +15 dBm low-power mode with GPIO-controlled switching. The module embeds all required passive components for SMPS, clocking (32 MHz TCXO + 32.768 kHz XO), and RF filtering - validated per ETSI EN 300 220, FCC Part 15, and ARIB STD-T-108.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | Dual-core Arm® Cortex®-M4 @ 48 MHz + Cortex®-M0+ @ 48 MHz - enables parallel protocol stack and application processing |
| Memory | 256 KB flash + 64 KB SRAM (32 KB SRAM1 + 32 KB SRAM2) - sufficient for LoRaWAN® Class C and secure OTA updates |
| Rx Sensitivity | –148 dBm @ LoRa® (10.4 kHz, SF12) - enables ultra-long-range reception in weak-signal environments |
| Transmit Power | Programmable up to +22 dBm (HP mode) or +15 dBm (LP mode) - configurable via BIAS_HP/BIAS_LP control pins |
| Operating Voltage | 1.8 V to 3.6 V - compatible with single-cell Li-SOCl₂, Li-MnO₂, and 2xAA battery systems |
| Temperature Range | –40°C to +85°C - qualified for industrial outdoor metering and smart agriculture deployments |
| Regulatory Certifications | FCC ID YCP-32WL5MOCH01, IC 8976A-32WL5MOCH01, ARIB STD-T-108 - eliminates need for end-product RF re-certification |
Pinout & Package
LGA92 (10×10 mm) system-in-package with 92 solder balls; full RF shielding, integrated SMPS passives, and STSAFE-A110 footprint (not populated on this variant).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| ANT | RF Antenna Interface | Single-ended 50 Ω RF output requiring controlled-impedance trace; TOS ≤2 required for optimal Tx/Rx performance |
| BIAS_HP | High-Power PA Enable | GPIO-controlled signal activating +22 dBm transmit path; must be driven high for HP mode |
| BIAS_LP | Low-Power PA Enable | GPIO-controlled signal activating +15 dBm transmit path; must be driven high for LP mode |
| VR_PA | PA Voltage Regulator Input | Supplies regulated voltage to RF power amplifier; connects to internal SMPS output |
| VDDPA / VDDRF1V55 | RF Power Supply Rails | Dedicated 1.55 V and 3.3 V supplies for RF transceiver block - isolated from digital VDD |
| SW_CTL | External RF Switch Control | Enables external antenna switch selection between diversity antennas or Tx/Rx isolation paths |
Key Features
| Feature | Design Value |
|---|---|
| Dual-core Secure Execution | M4 core runs LoRaWAN® stack with AES-256/PKA acceleration; M0+ handles low-power scheduling and wake-up events |
| Regulatory-Ready RF Front-End | Embedded TCXO, matching network, IPD filter, and antenna interface - meets FCC/ETSI/ARIB without external tuning |
| Configurable RF Output Paths | Hardware-selectable +22 dBm (HP) or +15 dBm (LP) modes via BIAS_HP/BIAS_LP pins - no software reconfiguration needed |
| Ultra-Low-Power System | SMPS-integrated power management, 37 GPIOs with wake-up capability, and sub-μA deep-sleep current - extends battery life to >10 years |
| STSAFE-A110 Footprint | Pre-routed pads for optional secure element co-location - enables hardware-rooted key storage and secure boot verification |
Applications
| Smart Utility Metering | Industrial Asset Tracking |
|---|---|
Use Scenario: Battery-powered water/gas/electricity meters transmitting hourly consumption data over 5–15 km rural coverage. IC Role / Device Role / Timing Role: Sub-GHz SoC module handling LoRaWAN® Class C uplink/downlink, secure firmware update, and RTC-based time-stamped logging. Use Value: Eliminates RF design effort and regulatory re-testing; –148 dBm sensitivity ensures reliable reception in underground meter pits. | Use Scenario: Solar-powered GPS trackers monitoring container location and temperature/humidity in rail/sea logistics corridors. IC Role / Device Role / Timing Role: Dual-core processor executing GNSS parsing (M4) and low-power sleep/wake scheduling (M0+); RF transceiver sends compressed telemetry via Sigfox™. Use Value: +22 dBm HP mode maintains link budget over 8 km non-line-of-sight; integrated SMPS enables direct solar harvesting without external DC-DC. |
| Smart Agriculture Sensor Network | LPWAN-Based Smart City Infrastructure |
Use Scenario: Soil moisture, NPK, and ambient sensors deployed across 500-hectare farms, reporting daily via star topology to gateway. IC Role / Device Role / Timing Role: Sub-GHz radio module operating in W-MBus mode with adaptive data rate; M0+ core manages sensor polling intervals and duty cycling. Use Value: Hardware-accelerated BPSK demodulation reduces Rx current to 4.2 mA; 10×10 mm LGA92 footprint enables compact PCB layout in weatherproof enclosures. | Use Scenario: Streetlight controllers and waste bin fill-level monitors deployed citywide using LoRaWAN® public network infrastructure. IC Role / Device Role / Timing Role: Certified SiP module providing FCC/ISED-compliant transmission; STSAFE-A110 footprint allows future upgrade to secure join-server authentication. Use Value: Pre-certified RF path avoids 6–12 month certification delays; 37 GPIOs support direct connection to photocell, ultrasonic fill sensor, and relay drivers. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar multiprotocol LPWAN module applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STM32WLE5JC8U6 | QFN48 MCU-only (no SiP integration); requires external RF matching, TCXO, and antenna filter | Demands full RF design expertise and end-product FCC re-certification | Select when custom RF layout is required or cost-sensitive designs need component-level BOM control |
| RA4W1F20GHJ01 | Single-core Arm® Cortex®-M4; only supports (G)FSK; no LoRa® or sub-GHz PA; 128 KB flash | Limited to proprietary narrowband protocols; lacks regulatory certifications for LoRaWAN® deployment | Select for short-range FSK-based sensor networks where LoRa® range and standards compliance are unnecessary |
Compared with STM32WL5MOCH6STR, STM32WLE5JC8U6 shifts RF design responsibility to the customer and increases time-to-certification, while RA4W1F20GHJ01 omits LoRa® support and regulatory pre-approval - making STM32WL5MOCH6STR the only drop-in solution for certified, long-range, multi-protocol LPWAN endpoints.
Availability
STM32WL5MOCH6STR is available at Aetrix Electronics and suitable for smart utility metering, industrial asset tracking, and smart agriculture sensor networks requiring stable component supply, full regulatory compliance, and rapid time-to-market.
Supply support for STM32WL5MOCH6STR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, analog ICs, power management, and MEMS sensors for industrial, automotive, and IoT markets.
The STM32WL series targets certified, ultra-low-power LPWAN endpoints - integrating dual-core MCUs with sub-GHz radios, security accelerators, and regulatory-ready RF front-ends to eliminate RF design barriers for IoT developers.
FAQ
What regulatory certifications does the STM32WL5MOCH6STR hold?
The STM32WL5MOCH6STR carries full pre-certifications: FCC ID YCP-32WL5MOCH01 (USA), IC 8976A-32WL5MOCH01 (Canada), and ARIB STD-T-108 (Japan). These cover its 864–928 MHz operation under LoRa®, (G)FSK, and BPSK modulations at +22 dBm HP and +15 dBm LP output levels - enabling direct integration into end products without additional RF testing.
Does the STM32WL5MOCH6STR include STSAFE-A110 security hardware?
No, the STM32WL5MOCH6STR variant includes only the STSAFE-A110 footprint - not the physical secure element. STSAFE-A110 is populated only on the STM32WL5MOCH6S part number. This version provides mechanical and routing compatibility for future secure upgrade but requires external procurement and placement of the STSAFE-A110 chip if hardware-rooted key storage or secure boot is needed.
How is high-power vs. low-power RF transmission selected on this module?
Transmission power mode is selected by driving either BIAS_HP (for +22 dBm) or BIAS_LP (for +15 dBm) high, while keeping the other low. Both signals are GPIO-controllable; simultaneous assertion is prohibited. The VR_PA pin supplies regulated voltage to the active PA path, and VDDPA/VDDRF1V55 provide dedicated RF power rails - ensuring clean switching between modes without digital supply noise coupling.
Can the STM32WL5MOCH6STR operate without an external crystal?
Yes - the module integrates both a 32.768 kHz crystal for RTC/LSE and a 32 MHz TCXO for HSE, eliminating external crystal requirements. The TCXO provides temperature-stable clocking for RF modulation accuracy, and the LSE crystal enables precise real-time wake-up timing. Neither oscillator supports bypass mode; both must be used in their specified configurations per the reference manual RM0453.
STM32WL5MOCH6STR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 92-LGA
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- -
- Type:
- TxRx + MCU
- RF Family/Standard:
- General ISM < 1GHz
- Protocol:
- LoRaWAN 1.0, Sigfox, Wireless M-Bus
- Modulation:
- BPSK, FSK, GFSK, GMSK, MSK
- Frequency:
- 864MHz ~ 928MHz
- Data Rate (Max):
- 1.2kbps
- Power - Output:
- 22dBm
- Sensitivity:
- -148dBm
- Memory Size:
- 256kB Flash, 64kB SRAM
- Serial Interfaces:
- ADC, GPIO, I2C, I2S, SPI, IrDA, UART, USART
- GPIO:
- 37
- Voltage - Supply:
- 1.8V ~ 3.6V
- Current - Receiving:
- -
- Current - Transmitting:
- -
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 92-LGA (10x10)
STM32WL5MOCH6STR FAQ
1.How can I place an order for STM32WL5MOCH6STR through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32WL5MOCH6STR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32WL5MOCH6STR reliable?
The price and inventory of STM32WL5MOCH6STR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32WL5MOCH6STR is usually 5 days.
3.What payment methods are accepted for STM32WL5MOCH6STR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32WL5MOCH6STR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32WL5MOCH6STR?
STM32WL5MOCH6STR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32WL5MOCH6STR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32WL5MOCH6STR?
For technical support, including STM32WL5MOCH6STR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32WL5MOCH6STR requirements.
6.How does Aetrix verify that STM32WL5MOCH6STR is sourced from the original manufacturer or authorized distributors?
All STM32WL5MOCH6STR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32WL5MOCH6STR meets industry standards.
7.What is the process for return or replacement of STM32WL5MOCH6STR?
All STM32WL5MOCH6STR units undergo pre-shipment inspection (PSI). If there is an issue with STM32WL5MOCH6STR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32WL5MOCH6STR part is unused and in its original packaging.
Return procedure for STM32WL5MOCH6STR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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