STMicroelectronics STM6505RCABDG6F

Overview

STM6505RCABDG6F from STMicroelectronics is a dual push-button Smart Reset IC with user-adjustable setup delay, battery voltage monitoring (VBAT), and independent low-battery detect output (BLD). It features factory-programmable VCC reset thresholds (1.575–4.625 V), 2 mm × 2 mm TDFN8 package, open-drain RST/BLD outputs, and operates from 1.0 V to 5.5 V over –40 °C to +85 °C. Used in portable navigation devices for delayed hard-reset initiation and battery health indication.

For engineers reviewing the STM6505RCABDG6F datasheet, STM6505RCABDG6F pinout, STM6505RCABDG6F application, or STM6505RCABDG6F equivalent, key selection criteria include adjustable tSRC via external capacitor (2–15 s range), dual active-low SR0/SR1 inputs requiring simultaneous assertion, VBAT threshold fixed at 1.25 V with 8 mV hysteresis, and BLD open-drain output behavior under battery undervoltage conditions.

Technical Context

The STM6505 implements a combined dual-input Smart Reset logic where both SR0 and SR1 must be held low ≥ tSRC (programmed by SRC pin capacitor) to assert RST. Its internal VCC monitor asserts RST when supply falls below factory-set threshold (e.g., 2.93 V typ.), with tREC timeout after recovery. The BLD path uses a dedicated comparator on VBAT input referenced to 1.25 V, enabling battery-level detection independent of VCC regulation.

Unlike STM6502/6503/6504 variants, STM6505 integrates both SRC-based tSRC adjustment and VBAT monitoring in one TDFN8 device. Its RST output combines power-on reset, VCC undervoltage reset, and Smart Reset activation - all driving a single open-drain output. BLD operates exclusively on VBAT voltage level, with no interaction with RST timing or VCC monitoring logic.

Key Specifications

Pinout & Package

TDFN8 (DG) package: 2 mm × 2 mm × 0.75 mm body, 0.5 mm pitch, exposed thermal pad (not electrically connected). Pin 1 marked by dot; pin numbering counterclockwise from top-left corner.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual Smart Reset with battery monitoring applications.

Compared with STM6505RCABDG6F, STM6505RCABDG6 offers identical performance in standard packaging, while TPS3808G33DBVR omits Smart Reset logic and battery monitoring - making it unsuitable for applications requiring user-controlled hard reset or battery-aware system behavior.

Availability

STM6505RCABDG6F is available at Aetrix Electronics and suitable for smartphone power management, e-reader battery monitoring, portable navigation device (PND) recovery, and MP3 player system recovery requiring stable component supply across extended production lifecycles.

Supply support for STM6505RCABDG6F includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, sensors, and analog chips for industrial, automotive, and consumer markets.

The STM65xx Smart Reset family targets portable electronics requiring robust, hardware-based system recovery and battery health awareness - specifically engineered for mobile phones, e-books, and navigation devices where user-initiated reset reliability and power efficiency are critical.

FAQ

What is the function of the SRC pin on STM6505RCABDG6F?

The SRC pin connects to an external capacitor (CSRC) that sets the Smart Reset setup delay (tSRC) between 2 s and 15 s minimum. Charging current (~100 nA) into CSRC determines tSRC; ceramic or film capacitors ≥0.01 µF are required for accuracy. This pin enables hardware-configurable debounce without firmware involvement.

Can STM6505RCABDG6F monitor battery voltage while VCC is powered down?

No. The VBAT comparator requires VCC ≥1.575 V to operate. When VCC is absent or below this threshold, BLD output is invalid and VBAT monitoring is disabled. Battery voltage can only be reliably detected when the main supply is active and within specification.

How does the dual SR0/SR1 input logic differ from single-button Smart Reset ICs?

STM6505RCABDG6F requires both SR0 and SR1 to be asserted low simultaneously for ≥tSRC to trigger RST. This prevents accidental reset from single-button press or noise glitches. Single-input variants (e.g., STM6502) use only SR0, making them more susceptible to false triggers in noisy environments.

Is the BLD output compatible with a 1.8 V I/O domain?

Yes. BLD is an open-drain output with no internal pull-up; it can be pulled up to any voltage ≤5.5 V. For 1.8 V systems, connect an external pull-up resistor to 1.8 V. Output leakage is <100 nA, ensuring compatibility without level-shifting circuitry.