STMicroelectronics STM6510RCACDG6F

Overview

STM6510RCACDG6F from STMicroelectronics is a dual push-button Smart Reset™ IC with capacitor-adjustable reset setup delay (tSRC) and reset pulse duration (tREC), factory-programmable VCC threshold (e.g., 2.925 V ±2.5%), active-low open-drain RST output, and 1.4 µA supply current at 3.0 V. It operates from 1.0 V to 5.5 V across –40 °C to +85 °C and is used in portable electronics requiring delayed hard-reset activation after sustained button press.

For engineers reviewing the STM6510RCACDG6F datasheet, STM6510RCACDG6F pinout, STM6510RCACDG6F application, or STM6510RCACDG6F equivalent, this page delivers verified pin functions, capacitor-programmed timing equations (tSRC = 10–20 × CSRC in seconds; tREC = 10–20 × CtREC in milliseconds), VCC undervoltage monitoring behavior, TDFN8 package layout, and dual-SR input coordination logic for interrupt-assisted system recovery.

Technical Context

The STM6510 implements dual active-low Smart Reset™ inputs (SR0/SR1) that must both be held low ≥ tSRC - programmable via external capacitor on SRC - before asserting RST. Its internal comparator monitors VCC against a factory-set threshold (S option = 2.925 V typ.), triggering RST when VCC falls below VRST and holding it active for tREC after VCC recovers.

Reset timeout tREC is independently adjustable via capacitor on TRECADJ pin; both tSRC and tREC use precision 100 nA current sources for linear scaling. The device features internal 65 kΩ pull-ups on SR0/SR1, open-drain RST with 0.3 V VOL at 0.1 mA, and guaranteed glitch immunity equal to tSRC during simultaneous SR assertion.

Key Specifications

Pinout & Package

TDFN8 package: 2 mm × 2 mm footprint, 0.5 mm pitch, no thermal pad, RoHS-compliant, 8-lead surface-mount outline per Doc ID 16788 Rev 2 Figure 12.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual push-button reset applications.

Compared with MAX6816EUT+T and TPS3808G18DBVR, the STM6510RCACDG6F uniquely integrates dual-button coordination, capacitor-tunable tSRC/tREC, and factory-programmable VCC thresholds - enabling hardware-level reset policy enforcement without MCU intervention.

Availability

STM6510RCACDG6F is available at Aetrix Electronics and suitable for mobile phones, e-book readers, and portable navigation devices requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.

Supply support for STM6510RCACDG6F includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing analog, microcontroller, power, and sensor solutions for automotive, industrial, and consumer markets.

The STM65xx Smart Reset™ product line targets portable electronics needing robust, low-power hardware reset management - specifically engineered to replace firmware-based reset logic with deterministic, capacitor-configurable timing and dual-input coordination.

FAQ

What is the minimum recommended value for CSRC and CtREC capacitors?

The datasheet specifies 0.01 µF minimum for CSRC and 0.001 µF minimum for CtREC to ensure timing accuracy. Lower values increase sensitivity to leakage current and PCB parasitics, potentially causing tSRC or tREC deviation beyond ±50% tolerance. Ceramic or film capacitors with low DC leakage are mandatory.

How does the STM6510 handle simultaneous SR0/SR1 assertion versus single-input scenarios?

Both SR0 and SR1 must be held low for ≥ tSRC to trigger RST; if only one is asserted, no reset occurs. This dual-input requirement prevents false resets from stray noise or single-button shorts. For single-button use, SR0 and SR1 are tied together per Figure 4 - effectively converting the device into a single-input Smart Reset™ with identical timing behavior.

Can the NC pin be left floating, or must it be connected?

The NC pin is not internally bonded and must be connected to VSS (ground) as explicitly stated in the datasheet's pin description section. Leaving it floating may cause unpredictable ESD susceptibility or noise coupling due to its physical proximity to sensitive analog nodes like SRC and TRECADJ.

What happens to RST during VCC ramp-up at power-on?

During VCC ramp-up, RST remains asserted (low) until VCC exceeds the factory-set VRST threshold by ≥100 mV and stays above it for ≥20 µs, after which RST deasserts. This built-in power-on reset (POR) function ensures the host processor starts only after stable supply is established - no external POR circuit required.