STMicroelectronics STM6513REIEDG6F

Overview

STM6513REIEDG6F from STMicroelectronics is a dual push-button Smart Reset IC with user-selectable reset setup delay (2/6/10 s min), dual independent reset outputs (RST1 active-high push-pull, RST2 active-low open-drain), and factory-programmable VCC monitoring thresholds (1.575–4.625 V typ.). It delivers 3 µA supply current, operates from 1.0 V to 5.5 V, and targets handheld electronics requiring robust, glitch-immune hard reset initiation.

For engineers reviewing the STM6513REIEDG6F datasheet, STM6513REIEDG6F pinout, STM6513REIEDG6F application, or STM6513REIEDG6F equivalent, key selection considerations include tSRC delay configuration via TSR pin logic state, capacitor-adjustable tREC1 on TRECADJ, dual-output timing coordination, and factory-set tREC2 (210 ms typ.) for PS_hold assertion in microprocessor reset sequences.

Technical Context

The device implements dual synchronized Smart Reset inputs (SR0/SR1) requiring simultaneous low assertion for ≥tSRC before asserting both RST1 and RST2. The tSRC delay is selected by TSR pin voltage level: grounded (2 s), floating (6 s), or tied to VCC (10 s), all minimum values with temperature and supply voltage dependence confirmed per Figure 6.

RST1 reset pulse duration (tREC1) is externally programmable via capacitor CtREC on TRECADJ (10–10,000 ms range), while RST2's tREC2 is factory-set to 210 ms (option E) or 360 ms (option F). VCC undervoltage detection triggers reset assertion when VRST threshold is crossed, with hysteresis (0.5–1% depending on option) and guaranteed 20 µs response delay.

Key Specifications

Pinout & Package

TDFN8 package: 2 mm × 2 mm × 0.75 mm body, 0.5 mm lead pitch, exposed thermal pad (not electrically connected), pin 1 marked by dot.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual Smart Reset applications.

Compared with STM6513REIEDG6F, STM6512REIEDG6F reduces input flexibility but maintains identical timing precision and package compatibility, while MAX6369KA26+T trades configurability for simpler implementation and lower BOM count in basic reset supervision roles.

Availability

STM6513REIEDG6F is available at Aetrix Electronics and suitable for smartphone power sequencing, eBook system recovery, MP3 player hard reset, and portable navigation device stability requiring stable component supply across industrial temperature ranges (–40 °C to +85 °C).

Supply support for STM6513REIEDG6F includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing analog, microcontroller, power, and sensor solutions for industrial, automotive, and consumer markets.

The STM65xx Smart Reset family targets handheld and portable electronics needing robust, low-power, user-controllable reset supervision-specifically addressing instability caused by accidental button presses or supply transients in battery-operated devices.

FAQ

What is the minimum VCC voltage required for RST1 to function correctly?

RST1 requires VCC ≥ 1.2 V to guarantee valid active-high output voltage (VOH ≥ 0.8 × VCC) per Table 5. Below 1.2 V, RST1 output is undefined; however, RST2 remains functional down to VCC = 1.0 V, enabling basic reset assertion even under deep brownout conditions.

How does the TSR pin affect tSRC tolerance over temperature and supply voltage?

Per Figure 6, tSRC varies with temperature and VCC: at VCC = 3.3 V and –40 °C to +85 °C, tSRC ranges from 2.0–2.8 s (TSR = VSS), 6.0–7.8 s (TSR = floating), and 10.0–13.5 s (TSR = VCC). Designers must account for this variation when specifying minimum hold times for user reset actions.

Can TRECADJ be left unconnected if only tREC2 is needed?

No. TRECADJ must be connected to a defined voltage (typically VSS via 0.1 µF capacitor) even when tREC1 is unused. Leaving it floating risks noise coupling, timing inaccuracy, or erratic tREC1 behavior due to its high-impedance sensing node-STMicroelectronics explicitly recommends decoupling it to VSS.

What is the maximum allowable leakage for CtREC to ensure tREC1 accuracy?

CtREC must exhibit ≤1 nA leakage at operating temperature and voltage. Ceramic or film capacitors are mandated; electrolytic or high-leakage dielectrics cause significant tREC1 drift. PCB layout must minimize surface contamination and humidity exposure near TRECADJ to preserve 100 nA-level charging current integrity.