STMicroelectronics STM6513SEIEDG6F

Overview

STM6513SEIEDG6F from STMicroelectronics is a dual push-button Smart Reset IC with user-selectable extended reset setup delay (2/6/10 s min), dual independent reset outputs (RST1 active-high push-pull, RST2 active-low open-drain), and factory-programmable V_CC monitoring thresholds (1.575–4.625 V typ.). It operates from 1.0 V to 5.5 V, draws only 3 µA supply current, and targets portable electronics requiring robust, glitch-immune manual reset control.

For engineers reviewing the STM6513SEIEDG6F datasheet, STM6513SEIEDG6F pinout, STM6513SEIEDG6F application, or STM6513SEIEDG6F equivalent, this device delivers deterministic delayed reset validation, capacitor-adjustable tREC1 pulse duration, industrial-grade temperature operation (–40 °C to +85 °C), and TDFN8 package compatibility for space-constrained handheld designs.

Technical Context

The STM6513 implements dual synchronized Smart Reset logic: both SR0 and SR1 must be held low simultaneously for ≥tSRC (programmed via TSR pin logic state) before asserting RST1 and RST2. The tSRC delay is fixed at 2 s (TSR = GND), 6 s (TSR = floating), or 10 s (TSR = V_CC), all minimum values verified across –40 °C to +85 °C and 1.0–5.5 V.

RST1 reset pulse width (tREC1) is externally adjustable via capacitor on TRECADJ (e.g., 100 nF → ~1.5 s), while RST2 pulse width (tREC2) is factory-set to 210 ms (option E) or 360 ms (option F). V_CC monitoring uses a precision bandgap reference with ±2.5% threshold tolerance over temperature and supports eight factory-configured VRST options.

Key Specifications

Pinout & Package

TDFN8 (DG) package: 2 mm × 2 mm × 0.75 mm, 0.5 mm pitch, exposed thermal pad (not electrically connected), RoHS compliant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual delayed reset supervisor applications.

Compared with MAX6326–MAX6328 and TPS3808G18, the STM6513SEIEDG6F uniquely provides dual synchronized Smart Reset inputs with hardware-selectable tSRC delay and independent RST1/RST2 timing - enabling robust, firmware-free recovery in portable consumer electronics where accidental resets must be eliminated.

Availability

STM6513SEIEDG6F is available at Aetrix Electronics and suitable for smartphone power sequencing, e-book system recovery, portable navigation device reset, and MP3 player fault recovery requiring stable component supply and guaranteed industrial-temperature operation.

Supply support for STM6513SEIEDG6F includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing analog, digital, and mixed-signal ICs for automotive, industrial, and consumer markets.

The STM65xx Smart Reset family targets portable electronics requiring glitch-immune manual reset with programmable delay and dual-output coordination - specifically engineered for mobile phones, e-books, and navigation devices where system stability depends on precise reset timing.

FAQ

What is the minimum valid V_CC for RST1 to function as an active-high push-pull output?

RST1 requires V_CC ≥ 1.2 V to guarantee valid active-high output (VOH ≥ 0.8 × V_CC with 0.05 mA source current). Below 1.2 V, RST1 output is not specified - though RST2 remains functional down to 1.0 V as an active-low open-drain output per datasheet Table 5.

How is the tREC1 reset pulse duration calculated from the external capacitor value?

tREC1 (ms) = 15,000 × CtREC (µF), typ., with ±33% variation (10,000–20,000 × CtREC). For example, a 0.01 µF ceramic capacitor yields tREC1 ≈ 150 ms (min 100 ms, max 200 ms). Use low-leakage film or NP0/C0G ceramics placed adjacent to TRECADJ.

Can SR0 and SR1 be used independently, or must they always be asserted together?

Both SR0 and SR1 must be held low simultaneously for ≥tSRC to assert RST1/RST2. If only one is used, the unused input must be permanently tied to VSS (GND) - floating SR pins cause undefined behavior and potential false triggering per datasheet Section 3.3.

What is the purpose of the 0.1 µF capacitor recommended between TSR and VSS when TSR is left floating?

When TSR is floating to select 6 s tSRC, the 0.1 µF capacitor suppresses noise-induced glitches that could falsely shift the TSR logic state. This improves system immunity to ESD and board-level transients, ensuring tSRC remains stable at 6 s without unintended transitions to 2 s or 10 s modes.