STMicroelectronics STM6513VEIEDG6F

Overview

STM6513VEIEDG6F from STMicroelectronics is a dual push-button Smart Reset IC with user-selectable extended setup delay (2/6/10 s min), capacitor-adjustable reset pulse duration (tREC1), and dual active-high push-pull (RST1) and active-low open-drain (RST2) outputs. It monitors VCC from 1.575 V to 4.625 V (factory-programmed threshold), operates from 1.0 V to 5.5 V, draws only 3 µA, and targets portable electronics requiring robust, glitch-immune manual reset control.

For engineers reviewing the STM6513VEIEDG6F datasheet, STM6513VEIEDG6F pinout, STM6513VEIEDG6F application, or STM6513VEIEDG6F equivalent, this device delivers deterministic delayed-reset validation, dual independent reset outputs with distinct drive types, programmable timeout timing, and industrial-grade temperature operation (–40 °C to +85 °C) in a space-constrained TDFN8 package.

Technical Context

The STM6513 implements dual synchronized Smart Reset logic: both SR0 and SR1 must be held low simultaneously for the full tSRC delay (selected via TSR pin logic state) before asserting RST1 and RST2. Its internal voltage monitor triggers reset on VCC drop below factory-set VRST, holding outputs active for tREC1 (capacitor-adjusted) and tREC2 (factory-programmed 210 ms typ.).

TSR is a DC-configured three-state input (VSS = 2 s, floating = 6 s, VCC = 10 s min.), not dynamically switched; TRECADJ accepts an external capacitor (0.001–0.112 µF) to set tREC1 from 10 ms to 2240 ms; RST1 drives high actively while RST2 requires external pull-up and sinks current only.

Key Specifications

Pinout & Package

TDFN8 package: 2 mm × 2 mm × 0.75 mm, 0.5 mm pitch, exposed thermal pad (not electrically connected), RoHS compliant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-push-button delayed reset applications.

Compared with MAX6369EUT+T and TPS3808G18DBVR, the STM6513VEIEDG6F uniquely combines dual synchronized push-button validation, three selectable tSRC delays, capacitor-tunable tREC1, and dual-drive reset outputs - making it the sole fit for portable systems demanding robust, user-intent-verified hard reset with minimal external components.

Availability

STM6513VEIEDG6F is available at Aetrix Electronics and suitable for mobile phones, e-books, and portable navigation devices requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.

Supply support for STM6513VEIEDG6F includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, specializing in microcontrollers, power management, analog, and sensor solutions for automotive, industrial, and consumer markets.

The STM65xx Smart Reset family was designed specifically for portable electronics requiring immunity to accidental reset, deterministic delayed manual recovery, and integrated VCC monitoring - eliminating discrete reset ICs and RC timing networks.

FAQ

What is the minimum VCC required for RST2 to function as an active-low output?

RST2 remains functional as an active-low open-drain output down to VCC = 1.0 V. At this voltage, it can sink 0.1 mA with VOL ≤ 0.3 V, ensuring compatibility with low-voltage MCUs and PMICs in deep-brownout conditions. This specification is guaranteed across the full industrial temperature range (–40 °C to +85 °C).

How does the TSR pin affect tSRC tolerance over temperature and voltage?

At TSR = VSS, tSRC is guaranteed ≥2 s across –40 °C to +85 °C and VCC = 1.0–5.5 V; measured typical values range from 2.1 s to 2.9 s depending on VCC and temperature. The datasheet provides Figure 6 showing tSRC vs. temperature curves for each TSR configuration, confirming monotonic behavior with no inversion or discontinuity.

Can SR0 and SR1 be used independently, or must they always be asserted together?

SR0 and SR1 must be held low simultaneously for the full tSRC duration to trigger reset outputs. If only one is asserted, no reset occurs - the device ignores partial activation. For single-button use, tie the unused input permanently to VSS; floating either SR pin is not permitted and may cause undefined behavior.

What capacitor type and value are recommended for TRECADJ to achieve tREC1 = 500 ms?

To achieve tREC1 ≈ 500 ms, use a 0.028 µF (28 nF) ceramic capacitor with ≤10 nA leakage, placed within 2 mm of TRECADJ and VSS. Table 2 confirms 0.028 µF yields 280–560 ms (min–max); actual value depends on capacitor tolerance and temperature. Avoid electrolytic or high-leakage dielectrics, as they degrade timing accuracy.