STMicroelectronics STM6519APAAUB6F

Overview

STM6519APAAUB6F from STMicroelectronics is a single-pin Smart Reset™ supervisory IC that implements a factory-programmed 7.5 s extended setup delay (tSRC) and fixed 210 ms reset pulse duration (tREC), operating from 2.0 V to 5.5 V with only 1 μA supply current. It features active-low SR input with internal pull-up, active-low open-drain RST output with optional internal pull-up, and operates across –40 °C to +85 °C in UDFN6 package - used for reliable push-button-initiated hard resets in portable consumer electronics.

For engineers reviewing the STM6519APAAUB6F datasheet, STM6519APAAUB6F pinout, STM6519APAAUB6F application, or STM6519APAAUB6F equivalent, this device delivers deterministic delayed reset timing, test-mode entry via overvoltage on SR, glitch-immune push-button interface, and voltage-domain flexibility - critical for mobile system stability and user-intent discrimination between interrupt and full reset.

Technical Context

The STM6519APAAUB6F integrates a precision programmable timer that triggers RST only after SR remains asserted for exactly 7.5 s (typ.), with ±20% variation over temperature. Its logic detects V(SR) ≥ VCC + 1.1 V to enter test mode, initiating a 42 ms (typ.) shortened tSRC-INI counter and enabling rapid validation without full delay cycles.

Reset output behavior is strictly defined by configuration: RST asserts low after tSRC expiry and holds for precisely 210 ms (typ., ±30%), independent of SR release timing - eliminating software dependency for reset duration. The device supports mixed-voltage domain operation via fixed SR input thresholds and open-drain RST with optional pull-up, ensuring interoperability with microcontrollers at different logic levels.

Key Specifications

Pinout & Package

UDFN6 package: 1.00 mm × 1.45 mm, 0.5 mm pitch, 6-terminal leadless plastic package with exposed thermal pad (not bonded); RoHS-compliant ECOPACK®2.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar push-button supervised reset applications.

Compared with STM6519APAAUB6F, the AHARUB6F offers shorter delay and no fixed pulse, trading timing certainty for responsiveness; the APARUB6F retains identical delay but removes tREC, requiring firmware coordination for pulse termination - making the APAAUB6F optimal for systems needing guaranteed, autonomous reset timing.

Availability

STM6519APAAUB6F is available at Aetrix Electronics and suitable for smartphone power management, e-reader system recovery, portable GPS navigation, and Bluetooth headset firmware recovery requiring stable component supply across industrial temperature ranges and long-lifecycle production programs.

Supply support for STM6519APAAUB6F includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing analog, microcontroller, power, and sensor solutions for industrial, automotive, and consumer markets.

The STM6519 belongs to ST's Smart Reset™ supervisory IC product line, engineered specifically to replace mechanical reset buttons with intelligent, delay-configurable, low-power push-button interfaces for portable and battery-operated systems.

FAQ

What is the exact tSRC and tREC timing for STM6519APAAUB6F?

The STM6519APAAUB6F has a factory-programmed Smart Reset delay (tSRC) of 7.5 s (typical), with ±20% variation over –40 °C to +85 °C. Its reset output pulse duration (tREC) is fixed at 210 ms (typical), with ±30% tolerance. These values are laser-trimmed during production and cannot be modified in-circuit.

Can the SR input be used without an external pull-up resistor?

Yes - STM6519APAAUB6F includes an internal 65 kΩ pull-up resistor on the SR pin, so no external component is required for basic operation. This ensures SR defaults to logic high when unpressed, enabling clean low-to-high transition detection and eliminating floating-input risk.

How does test mode activation work, and what happens when it's triggered?

Test mode activates when SR is driven to ≥ VCC + 1.1 V (e.g., via external voltage source). The device then asserts RST for 42 ms (tSRC-INI), providing immediate visual or logic feedback. Subsequent SR toggles use shortened tSRC-SHORT (7.5 s ÷ 128 ≈ 59 ms), enabling rapid functional verification without waiting for full delay cycles.

Is the RST output compatible with 1.8 V microcontrollers?

Yes - configured as open-drain with optional internal pull-up, RST can drive 1.8 V logic domains when pulled to 1.8 V externally. The output leakage current is ≤ ±0.1 µA, and VOL remains ≤ 0.3 V at 1 mA sink, ensuring valid low-level signaling across voltage domains without level shifters.