STMicroelectronics STM6519APARUB6F

Overview

STM6519APARUB6F from STMicroelectronics is a single-pin, push-button Smart Reset™ supervisor IC designed for delayed, glitch-immune system reset control in portable electronics. It features a factory-programmed Smart Reset delay (tSRC) of 7.5 s (typ.), active-low open-drain RST output with no tREC option (push-button controlled pulse width), operates from 2.0 V to 5.5 V, draws only 1 µA supply current, and uses UDFN6 (1.00 mm × 1.45 mm) packaging.

For engineers reviewing the STM6519APARUB6F datasheet, STM6519APARUB6F pinout, STM6519APARUB6F application, or STM6519APARUB6F equivalent, key selection criteria include configurable tSRC timing, test mode entry via SR overvoltage, undervoltage-safe RST high-Z behavior, and compatibility with mixed-voltage domain designs where SR and VCC are isolated.

Technical Context

The STM6519 implements a precision digital timer that triggers RST assertion only after SR remains low for the full 7.5 s (typ.) tSRC delay-rejecting short button presses (<100 ms) and ensuring robust reset initiation. Its logic includes dedicated test mode entry (VTEST = VCC + 1.4 V) with shortened tSRC-INI (42 ms typ.) and tSRC-SHORT (tSRC/128), enabling in-system validation without full power cycling.

Reset output behavior is strictly push-button dependent: RST de-asserts immediately upon SR release (no fixed tREC), making it ideal for applications requiring user-controlled reset duration. The device guarantees high-impedance RST during VCC undervoltage conditions and supports optional internal pull-up resistors on both SR (65 kΩ) and RST (65 kΩ), eliminating external components in many layouts.

Key Specifications

Pinout & Package

STM6519APARUB6F is housed in a 6-pin UDFN package (1.00 mm × 1.45 mm, 0.5 mm pitch) with exposed thermal pad. Pin 1 is marked by a dot; Pins 5 and 6 are not bonded and must be connected to VSS for mechanical stability and EMI control.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar Smart Reset supervisor applications.

Compared with STM6519APARUB6F, the AHARUB6F reduces tSRC by 3.5 s (46%) for quicker recovery, while ALARUB6F provides a 1.5 s (20%) reduction with minimal trade-off in glitch immunity - both retain identical supply range, package, and open-drain RST behavior.

Availability

STM6519APARUB6F is available at Aetrix Electronics and suitable for mobile phones, e-readers, and portable navigation devices requiring stable component supply, long-lifecycle support, and RoHS-compliant packaging.

Supply support for STM6519APARUB6F includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, delivering innovative solutions across automotive, industrial, and consumer markets with strong focus on power efficiency and reliability.

The STM6519 belongs to ST's Smart Reset™ supervisor product line, engineered specifically for portable electronics requiring robust, single-button hardware reset with programmable delay and mixed-voltage domain interoperability.

FAQ

What is the exact tSRC value for STM6519APARUB6F and how is it programmed?

The STM6519APARUB6F has a factory-programmed Smart Reset delay (tSRC) of 7.5 seconds (typical), with ±20% variation over temperature (-40 °C to +85 °C). This value is laser-trimmed during final test and cannot be modified in the field. It is selected via part number coding ('P' = 7.5 s) and verified per Table 6 in the official datasheet DocID022111 Rev 7.

Does STM6519APARUB6F provide a fixed reset pulse width (tREC)?

No. The 'R' in the part number suffix (APARUB6F) explicitly denotes "push-button controlled" operation with no defined tREC. RST remains asserted only while SR is held low and de-asserts immediately upon SR release - no factory-programmed timeout is active. This differs from variants ending in 'A', 'B', or 'E' which embed tREC values.

Can STM6519APARUB6F operate with SR and VCC in different voltage domains?

Yes - its open-drain RST output and fixed SR input logic thresholds (VIL ≤ 0.3 V, VIH ≥ 0.85×VCC) allow safe operation across voltage domains. However, VCC must power up before or simultaneously with SR voltage to prevent inadvertent test mode entry (VSR > VCC + 1.4 V), as confirmed in Section 4 and Figure 5 of the datasheet.

What is the purpose of Pins 5 and 6 on the UDFN6 package?

Pins 5 and 6 are not electrically bonded to the die and serve only mechanical and thermal functions. ST's datasheet (Section 2, Table 1) mandates connecting both to VSS to enhance thermal dissipation, reduce package warpage during reflow, and suppress noise coupling - they are not optional floating terminals.