STMicroelectronics STM6520AQRRDG9F

Overview

STM6520AQRRDG9F from STMicroelectronics is a dual push-button Smart Reset™ supervisor IC with user-selectable extended reset setup delay (tSRC = 7.5 s or 12.5 s typ.), active-low open-drain RST1 and active-high push-pull RST2 outputs, 1.65–5.5 V operating range, and 1.5 µA supply current at 3.0 V. It enables delayed hard-reset activation in portable consumer electronics where inadvertent short button presses must be ignored.

For engineers reviewing the STM6520AQRRDG9F datasheet, STM6520AQRRDG9F pinout, STM6520AQRRDG9F application, or STM6520AQRRDG9F equivalent, this device supports dual-input coordinated reset assertion, push-button–controlled pulse duration (no fixed minimum), undervoltage immunity down to 1.0 V output validity, and TDFN8 (2 mm × 2 mm) footprint compatibility for space-constrained handheld designs.

Technical Context

The STM6520 implements dual active-low Smart Reset™ inputs (SR0, SR1) requiring simultaneous assertion for tSRC before both RST1 and RST2 activate. Its internal oscillator-driven timer uses DSR pin logic (VSS or VCC) to select between two tSRC options-7.5 s or 12.5 s typ.-with ±1.5 s variation over temperature and voltage.

No power-on reset is generated; reset pulse duration is fully determined by push-button hold time. Outputs deassert immediately upon release of either SR input. Input glitch immunity equals tSRC when both SR inputs are low, otherwise infinite, eliminating false triggers from transient noise.

Key Specifications

Pinout & Package

TDFN8 package: 2 mm × 2 mm × 0.75 mm body, 0.5 mm pitch, exposed pad not electrically connected (NC). RoHS-compliant, ECOPACK® grade.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-input delayed reset applications.

Compared with MAX6816 and TPS3808G33, the STM6520AQRRDG9F uniquely delivers dual coordinated push-button inputs, user-selectable multi-second delays, and complementary active-low/active-high outputs-enabling intentional, user-controlled hard resets impossible with single-input supervisors or voltage monitors.

Availability

STM6520AQRRDG9F is available at Aetrix Electronics and suitable for mobile phones, e-books, and portable navigation devices requiring stable component supply, long-lifecycle support, and RoHS-compliant TDFN packaging.

Supply support for STM6520AQRRDG9F includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing analog, digital, and mixed-signal ICs for automotive, industrial, and consumer markets.

The STM65xx series is ST's dedicated Smart Reset™ product line, engineered specifically for portable electronics requiring user-initiated, glitch-immune, multi-second delayed reset functionality without software dependency.

FAQ

Does STM6520AQRRDG9F generate a power-on reset (POR) signal?

No. The STM6520AQRRDG9F explicitly omits power-on reset functionality. Reset outputs activate only after both SR0 and SR1 are held low for the selected tSRC duration (7.5 s or 12.5 s typ.). This design eliminates spurious resets during power-up sequencing and ensures reset is strictly user-initiated.

Can SR0 or SR1 be used independently, without the other?

Yes. If only one push-button is required, the unused Smart Reset™ input must be permanently tied to VSS (ground) per ST's application guidance. The device will then respond to the active-low assertion of the connected input alone-but still requires the full tSRC delay before asserting RST1/RST2.

What is the maximum sink current capability of the RST1 open-drain output?

RST1 guarantees VOL ≤ 0.3 V while sinking 3.2 mA at VCC ≥ 4.5 V, 2.5 mA at VCC ≥ 3.3 V, and 1 mA at VCC ≥ 1.65 V. External pull-up voltage and resistance must be selected to ensure these conditions are met for reliable microcontroller reset assertion.

Is the DSR pin intended for dynamic control during system operation?

No. DSR is a DC configuration pin designed to be statically tied to either VSS or VCC during PCB layout. It is not intended for runtime switching; changing DSR voltage mid-operation may cause undefined reset behavior or missed assertions due to internal logic metastability.