STMicroelectronics STM6522AAAADG6F

Overview

STM6522AAAADG6F from STMicroelectronics is a dual-input Smart Reset™ supervisor IC with capacitor-adjustable reset setup delay (tSRC), dual active-low open-drain RST outputs, and fixed logic thresholds for push-button reset validation. It operates from 1.65 V to 5.5 V, draws only 1.5 µA at 3.0 V, and supports industrial temperature range (–40 °C to +85 °C) in a TDFN8 package. Used in portable electronics requiring delayed hard-reset activation after sustained button press.

For engineers reviewing the STM6522AAAADG6F datasheet, STM6522AAAADG6F pinout, STM6522AAAADG6F application, or STM6522AAAADG6F equivalent, this page delivers verified pin functions, tSRC timing control via external capacitor, dual SR input coordination logic, open-drain RST output drive capability, and real-world use cases in mobile and embedded reset management.

Technical Context

The STM6522 implements dual independent Smart Reset™ inputs (SR0 and SR1) that must both be held low for a user-programmed setup delay (tSRC) - determined by an external capacitor on SRC - before asserting either RST1 or RST2. The tSRC delay ranges from 10×CSRC to 15×CSRC seconds (e.g., 10–15 s with 1 µF), with glitch immunity equal to tSRC when both inputs are active.

After tSRC expires, a factory-programmed reset timeout (tREC = 140–280 ms) is generated on both RST outputs. All logic thresholds (VIL = 0.3 V, VIH = 0.85×VCC) and supply current (1.5 µA typ. at 3.0 V) are specified across –40 °C to +85 °C and 1.65–5.5 V operation, with valid RST output levels down to 1.0 V supply.

Key Specifications

Pinout & Package

TDFN8 package: 2 mm × 2 mm × 0.75 mm, 0.5 mm pitch, no thermal pad, RoHS-compliant ECOPACK®.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-input programmable reset applications.

Compared with MAX6816EUT+T and TPS3808G125DBVR, the STM6522AAAADG6F uniquely supports dual coordinated push-button inputs with user-defined tSRC delay across 1.65–5.5 V, enabling intentional hard reset without MCU intervention - a capability absent in both alternatives.

Availability

STM6522AAAADG6F is available at Aetrix Electronics and suitable for mobile phones, e-books, and portable navigation devices requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.

Supply support for STM6522AAAADG6F includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing analog, microcontroller, power, and sensor solutions for industrial, automotive, and consumer markets.

The STM65xx Smart Reset™ family targets portable electronics requiring hardware-managed, delayed push-button reset functionality - specifically engineered to replace firmware-dependent reset logic with deterministic, low-power, capacitor-timed supervision.

FAQ

What capacitor value should be used on the SRC pin to achieve a 5-second tSRC delay?

A 0.4 µF ceramic capacitor yields a nominal tSRC of 5 seconds (12.5 × 0.4 µF = 5 s typical), within the 10–15×CSRC range specified. Use X7R or C0G dielectric with ≤100 nA leakage; place it within 2 mm of SRC pin and route over solid ground plane to minimize parasitic discharge paths.

Can SR0 and SR1 be used independently, or must both be asserted to trigger reset?

Both SR0 and SR1 must be held low for ≥tSRC to assert RST1/RST2. If only SR0 is active, no reset occurs - this dual-input requirement prevents false triggers from single-button noise. The device does not support independent operation of either input as a standalone reset source.

Is an external pull-up resistor required on RST1 and RST2 outputs?

Yes - RST1 and RST2 are open-drain with no internal pull-up. A pull-up resistor (typically 4.7 kΩ to 10 kΩ) must be connected to the target reset rail voltage (e.g., 1.8 V or 3.3 V). The value is chosen based on rise time requirements and bus capacitance, per I_OL = 3.2 mA max at V_CC ≥ 4.5 V.

Does the STM6522 provide power-on reset (POR) functionality?

No - the STM6522AAAADG6F explicitly omits power-on reset. It is designed solely for push-button-initiated reset with programmable setup delay. System POR must be handled separately by another supervisor IC or integrated MCU feature; this omission reduces complexity and current draw in applications where POR is already managed.