STMicroelectronics STM795SM6E
- Part No.:
- STM795SM6E
- Manufacturer:
- STMicroelectronics
- Category:
- Supervisors
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
STM795SM6E.pdf
- Description:
- IC SUPERVISOR 1 CHANNEL 8SO
- Quantity:
- Payment:

- Shipping:

Inventory:4,572
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
STM795SM6E from STMicroelectronics is a 3 V supply voltage supervisor IC with integrated battery switchover and chip-enable gating for external low-power SRAM (LPSRAM). It provides active-low RST output, manual reset input (MR), VCC switch output (Vccsw), and conditioned chip-enable output (ECON) with 7 ns max propagation delay. Designed for industrial-grade embedded systems requiring non-volatile memory retention during power loss.
For engineers reviewing the STM795SM6E datasheet, STM795SM6E pinout, STM795SM6E application, or STM795SM6E equivalent, key selection criteria include guaranteed RST assertion down to VCC = 1.0 V, 0.4 µA typical battery supply current, chip-enable gating timing control, and SO8 package compatibility with LPSRAM interface requirements.
Technical Context
The STM795 implements a precision voltage comparator monitoring VCC against a 2.63 V reset threshold (VRST) with hysteresis, ensuring reliable reset assertion during brown-out conditions. Its internal logic asserts RST low when VCC drops below VRST, MR is pulled low, or after trec (200 ms typ) following power-up.
Unlike other family members (e.g., STM704/806), the STM795 omits watchdog timer and power-fail comparator (PFI/PFO) functions but adds dedicated E (chip-enable input) and ECON (conditioned chip-enable output) pins enabling controlled gating of LPSRAM access during reset transitions - critical for preventing write corruption in battery-backed memory systems.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Reset Threshold | 2.63 V ±1.5% - guarantees deterministic MCU reset initiation at defined VCC dropout level |
| Reset Timeout (trec) | 200 ms (typ) - ensures sufficient hold time for microprocessor initialization after power recovery |
| Battery Supply Current | 0.4 µA (typ) - minimizes backup battery drain during extended VCC outage |
| Chip-Enable Prop Delay | 7 ns (max) - enables precise timing alignment between reset release and LPSRAM access enable |
| Operating Temperature | –40 °C to +85 °C - supports industrial-grade reliability in harsh environments |
| VCC Switchover Voltage | 2.4 V (VSW) - triggers automatic VOUT sourcing from VBAT before critical MCU brown-out |
| RST Assertion Limit | Valid down to VCC = 1.0 V - maintains reset integrity even under severe undervoltage conditions |
Pinout & Package
STM795SM6E is housed in an 8-pin SO8 (Small Outline Integrated Circuit) package, measuring 4.9 mm × 3.9 mm × 1.75 mm, with 1.27 mm lead pitch and RoHS-compliant lead-free finish.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| P1: PFO | Power-fail output | Not implemented on STM795 - pin is no-connect per datasheet Table 3 |
| P2: VOUT | Supply output voltage | Switches between VCC and VBAT to power external LPSRAM; supports up to 75 mA load |
| P3: VCC | Main supply input | Primary 3 V system rail; monitored for reset threshold violation |
| P4: Vccsw | VCC switch output | Push-pull signal indicating VOUT source (high = battery, low = VCC); drives external PMOS gate |
| P5: VSS | Ground reference | Common return path for all internal circuitry and I/Os |
| P6: E | Chip-enable input | Enables conditional gating of ECON; must be low to allow ECON activation post-reset |
| P7: RST | Active-low reset output | Push-pull output asserted low during reset; compatible with standard MCU reset inputs |
| P8: ECON | Conditioned chip-enable output | Low only when E is low AND reset is de-asserted; prevents LPSRAM access during reset recovery |
Key Features
| Feature | Design Value |
|---|---|
| Chip-enable gating | 7 ns max propagation delay from E to ECON ensures tight timing control for LPSRAM write-enable sequencing |
| Battery switchover | Automatic VOUT sourcing from VBAT when VCC falls below 2.4 V, preserving SRAM data without software intervention |
| Low battery current | 0.4 µA typical draw extends coin-cell life to >10 years in standby backup mode |
| Reset assertion limit | Guaranteed RST low down to VCC = 1.0 V enables robust operation in deep brown-out scenarios |
| Industrial temperature range | –40 °C to +85 °C operation validated across full range supports deployment in automotive body electronics and industrial PLCs |
Applications
| Smart Meter Data Retention | Industrial PLC Memory Backup |
|---|---|
Use Scenario: Utility smart meters retain tariff and consumption logs during grid outages using coin-cell-backed SRAM. IC Role / Device Role / Timing Role: STM795SM6E monitors main 3.3 V rail and switches VOUT to VBAT within 1 µs of VCC drop below 2.4 V while asserting RST to halt CPU writes. Use Value: Prevents SRAM corruption by disabling LPSRAM access via ECON until reset completes and system state is stabilized. | Use Scenario: Programmable logic controllers maintain configuration and I/O state in volatile SRAM during factory power interruptions. IC Role / Device Role / Timing Role: Acts as dual-function supervisor: generates clean reset pulse and gates SRAM chip-enable with sub-10 ns timing accuracy relative to reset de-assertion. Use Value: Eliminates need for discrete logic or FPGA-based reset coordination, reducing BOM count and layout complexity. |
| Medical Infusion Pump Memory | Automotive Body Control Module |
Use Scenario: Infusion pumps store dosage history and calibration parameters in LPSRAM during battery-only operation. IC Role / Device Role / Timing Role: Provides fail-safe reset signaling and battery switchover while enforcing strict access control via E/ECON to prevent partial-write errors. Use Value: Meets IEC 62304 Class C software safety requirements by guaranteeing atomic memory state preservation during power transitions. | Use Scenario: BCMs retain door lock status and lighting profiles across ignition cycles using backup SRAM. IC Role / Device Role / Timing Role: Supervises 3 V domain, asserts RST during cranking-induced brown-outs, and enables SRAM access only after stable VCC recovery and reset timeout completion. Use Value: Ensures zero data loss during cold-cranking events where VCC dips to 1.2 V for up to 50 ms. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar supervisor-with-LPSRAM-gating applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STM795T | Same die, different marking; identical electrical specs and pinout; T suffix denotes tape-and-reel packaging | No functional difference - direct replacement in automated assembly | Select STM795T for SMT production lines requiring reel-fed placement |
| STM795S | Same die, different marking; identical electrical specs and pinout; S suffix denotes tube packaging | No functional difference - suitable for prototyping or low-volume hand-soldering | Select STM795S for engineering validation or small-batch builds |
Compared with STM795SM6E, both STM795T and STM795S share identical supervision functionality, timing behavior, and LPSRAM gating capability - differing only in packaging format and associated handling logistics, not electrical or thermal performance.
Availability
STM795SM6E is available at Aetrix Electronics and suitable for smart meter data retention, industrial PLC memory backup, and medical infusion pump memory requiring stable component supply with guaranteed long-term availability.
Supply support for STM795SM6E includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, specializing in microcontrollers, power management, analog ICs, and sensors for industrial, automotive, and consumer markets.
The STM795 belongs to ST's 3 V supervisor family designed specifically for non-volatile memory protection in battery-backed embedded systems - emphasizing ultra-low quiescent current, precise reset thresholds, and integrated LPSRAM interface control.
FAQ
What is the function of the ECON pin on STM795SM6E?
ECON is a conditioned chip-enable output that goes low only when both the E input is low and reset is de-asserted. It remains low for 15 µs or until E returns high, whichever occurs first. This ensures LPSRAM access is blocked during reset recovery, preventing partial writes or read-after-write hazards in battery-backed memory systems.
Does STM795SM6E include a watchdog timer?
No. The STM795SM6E does not include a watchdog timer - this feature is explicitly excluded per datasheet Section 2.3 ("Watchdog input (NOT available on STM704/795/806)"). Unlike STM690 or STM802, the STM795 prioritizes chip-enable gating and battery switchover over watchdog functionality.
Can STM795SM6E be used without a backup battery?
Yes. When no battery is used, connect both VBAT and VOUT to the main VCC rail. The device operates normally as a reset supervisor, asserting RST on VCC dropout and providing push-pull reset signaling - the battery switchover circuitry is safely disabled by equalizing VBAT and VCC.
What is the maximum load current supported on the VOUT pin?
VOUT supports up to 75 mA continuous output current when sourcing from VCC or VBAT. For higher loads, the Vccsw pin can drive an external PMOS transistor to extend current capability beyond 75 mA while maintaining precise switchover timing and low dropout characteristics.
STM795SM6E Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Type:
- Simple Reset/Power-On Reset
- Number of Voltages Monitored:
- 1
- Voltage - Threshold:
- 2.925V
- Output:
- Open Drain or Open Collector
- Reset:
- Active Low
- Reset Timeout:
- 140ms Minimum
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
STM795SM6E FAQ
1.How can I place an order for STM795SM6E through Aetrix?
Please submit a Request for Quotation (RFQ) for STM795SM6E on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM795SM6E reliable?
The price and inventory of STM795SM6E are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM795SM6E is usually 5 days.
3.What payment methods are accepted for STM795SM6E?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM795SM6E transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM795SM6E?
STM795SM6E orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM795SM6E order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM795SM6E?
For technical support, including STM795SM6E datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM795SM6E requirements.
6.How does Aetrix verify that STM795SM6E is sourced from the original manufacturer or authorized distributors?
All STM795SM6E products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM795SM6E meets industry standards.
7.What is the process for return or replacement of STM795SM6E?
All STM795SM6E units undergo pre-shipment inspection (PSI). If there is an issue with STM795SM6E, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM795SM6E part is unused and in its original packaging.
Return procedure for STM795SM6E:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
STM795SM6E Tags

-
MIC826SYMT-TR
Microchip Technology

-
APX803S-31SA-7
Diodes Incorporated

-
APX803L20-29SA-7
Diodes Incorporated
-
TPS3828-33DBVR
Texas Instruments

-
V6340RSP3B+
EM Microelectronic

-
EM6325CXSP5B-2.9+
EM Microelectronic

-
MCP120T-300I/TT
Microchip Technology

-
MCP130T-315I/TT
Microchip Technology

-
MCP120T-475I/TT
Microchip Technology

-
MCP111T-300E/TT
Microchip Technology

-
MCP120T-315I/TT
Microchip Technology

-
MCP809T-315I/TT
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

