STMicroelectronics STM805SM6F

Overview

STM805SM6F from STMicroelectronics is a 3 V industrial-grade microprocessor supervisory IC with active-high open-drain RST output, automatic battery switchover (VCC to VBAT), power-fail comparator (PFI/PFO), manual reset input (MR), and watchdog timer (WDI). It guarantees reset assertion down to VCC = 1.0 V and supports external LPSRAM backup in embedded systems requiring reliable power monitoring and non-volatile memory protection.

For engineers reviewing the STM805SM6F datasheet, STM805SM6F pinout, STM805SM6F application, or STM805SM6F equivalent, key selection criteria include its 200 ms typical reset timeout (trec), 1.6 s watchdog timeout, 0.4 µA battery supply current, push-pull PFO output, and SO8 package compatibility for space-constrained industrial control and data logging designs.

Technical Context

The STM805 implements a precision voltage reference and comparator to monitor VCC against a fixed reset threshold (VRST ≈ 2.63 V), asserting RST when VCC drops below VRST or MR is pulled low. Its internal trec generator ensures minimum 200 ms reset pulse width after power-up or fault recovery.

It integrates dual-supply path control: VOUT connects to VCC above VSW (2.4 V) and switches to VBAT below VSW via an internal P-channel MOSFET; Vccsw provides a push-pull logic signal indicating switchover state. The PFI/PFO comparator operates independently of reset logic, providing early power-fail warning at VPFI ≈ 2.5 V.

Key Specifications

Pinout & Package

STM805SM6F is housed in an 8-pin SO8 (Small Outline) package with 1.27 mm pitch, RoHS-compliant, surface-mount footprint suitable for automated assembly and thermal reliability in industrial PCBs.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar supervisor applications.

Compared with STM804SM6F and TPS3809K33DBVR, STM805SM6F uniquely combines open-drain RST for bus arbitration, integrated PFI/PFO for predictive power management, and automatic VBAT switchover-making it the sole option among the three supporting robust LPSRAM backup in industrial edge devices.

Availability

STM805SM6F is available at Aetrix Electronics and suitable for industrial data loggers, smart metering units, programmable logic controllers, and medical diagnostic devices requiring stable component supply and long-term lifecycle support.

Supply support for STM805SM6F includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, designing and manufacturing analog, microcontroller, power, and sensor solutions for industrial, automotive, and consumer markets.

The STM690/80x supervisor family targets embedded systems needing guaranteed power-on reset, brownout protection, and non-volatile memory backup-optimized for reliability in harsh industrial environments.

FAQ

What is the function of the Vccsw pin on STM805SM6F?

Vccsw is a push-pull output that goes high when VOUT switches from VCC to VBAT, and low when VOUT reconnects to VCC. It provides real-time indication of the active supply source, enabling firmware to manage SRAM access or disable peripherals during battery backup mode. Its logic level is synchronized with the internal switchover MOSFET state and supports direct connection to MCU GPIOs without external conditioning.

Can STM805SM6F operate without a backup battery?

Yes-STM805SM6F functions fully without VBAT. In this configuration, connect both VBAT and VOUT to VCC to disable switchover. All supervision features (reset, watchdog, PFI/PFO) remain active. The device draws only 40 µA from VCC in normal operation and guarantees RST assertion down to VCC = 1.0 V, making it suitable for battery-less industrial controllers where brownout resilience is required.

How does the watchdog timer interact with the manual reset (MR) input?

The watchdog timer is disabled while reset is asserted-whether triggered by MR, VCC drop, or watchdog timeout. When MR is pulled low, reset activates immediately and holds the watchdog counter reset. After MR returns high, the timer restarts only after reset de-asserts (i.e., after trec expires and VCC remains above VRST). This prevents spurious timeouts during manual recovery sequences and ensures deterministic watchdog behavior aligned with system reset state.

Is the PFO output compatible with 5 V logic systems?

No-PFO is a push-pull output referenced to VCC and operates within the VCC supply range (typically 2.7–5.5 V per datasheet absolute max ratings). When VCC = 3.3 V, PFO swings from 0 V to ~3.3 V. Direct interfacing with 5 V logic requires a level-shifter or open-drain buffer. However, PFO can drive 3.3 V MCU interrupts directly, and its 2.5 V PFI threshold remains valid regardless of VCC, supporting mixed-rail monitoring.