STMicroelectronics STM805TM6E

Overview

STM805TM6E from STMicroelectronics is a 3 V industrial-grade microprocessor supervisory IC with active-high open-drain RST output, automatic battery switchover, power-fail comparator (PFI/PFO), manual reset input (MR), and watchdog timer (1.6 s typ). It guarantees reset assertion down to VCC = 1.0 V and delivers 0.4 µA typical battery supply current for non-volatile SRAM backup in embedded control systems.

For engineers reviewing the STM805TM6E datasheet, STM805TM6E pinout, STM805TM6E application, or STM805TM6E equivalent, key selection criteria include its open-drain active-high reset architecture, 200 ms typical reset timeout (trec), VCC switchover at 2.4 V (VSW), PFI threshold of 1.25 V (VPFI), and compatibility with LPSRAM backup in power-loss scenarios.

Technical Context

The STM805TM6E integrates a precision voltage reference, dual comparators (reset and power-fail), a 1.6 s watchdog timer, and a P-channel MOSFET-based VCC/VBAT switchover switch. Its reset logic asserts RST high when VCC falls below VRST (2.63 V) or MR is pulled low, with guaranteed timing over –40 °C to +85 °C.

It features push-pull PFO and Vccsw outputs, open-drain RST (requiring external pull-up), and dedicated pins for battery-backed SRAM support: VOUT supplies switched power to LPSRAM, while Vccsw signals switchover status for external PMOS gate control up to 75 mA load.

Key Specifications

Pinout & Package

STM805TM6E is housed in an 8-pin SO8 (Small Outline Integrated Circuit) package, measuring 4.9 mm × 3.9 mm × 1.75 mm, with 1.27 mm lead pitch and RoHS-compliant lead-free finish.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar supervisor applications.

Compared with MAX809SEUR+T and TPS3808G125DBVR, STM805TM6E uniquely integrates battery switchover, PFI/PFO, and watchdog in one SO8 package-enabling complete power-monitoring and SRAM backup functionality without additional ICs or layout complexity.

Availability

STM805TM6E is available at Aetrix Electronics and suitable for industrial PLC controllers, smart meter data loggers, medical infusion pumps, and automotive body control modules requiring stable component supply across extended temperature ranges and long product lifecycles.

Supply support for STM805TM6E includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing silicon solutions for automotive, industrial, and consumer markets since 1987.

The STM690/704/795/802/804/805/806 family was engineered specifically for microprocessor supervision in battery-backed embedded systems-prioritizing ultra-low quiescent current, guaranteed reset behavior under brownout, and seamless SRAM power management.

FAQ

What is the function of the Vccsw pin on STM805TM6E?

Vccsw is a push-pull output that goes high when VOUT switches from VCC to VBAT, and low when VOUT returns to VCC. It is designed to drive the gate of an external PMOS transistor, enabling higher current (>75 mA) battery backup for LPSRAM where the internal 100 Ω switch is insufficient. This pin eliminates need for discrete logic-level translation in high-current switchover designs.

Can STM805TM6E operate without a backup battery connected?

Yes. When no battery is used, VBAT and VOUT must both be connected to VCC. In this configuration, the device functions as a standard 3 V supervisor with RST, MR, PFI/PFO, and watchdog-retaining full reset guarantee down to VCC = 1.0 V and 200 ms trec. Battery switchover logic remains inactive but does not impair core supervision functionality.

Why does STM805TM6E use an open-drain RST output instead of push-pull?

The open-drain RST allows flexible voltage-level interfacing: an external pull-up resistor sets the logic-high voltage (e.g., 3.3 V or 5 V), enabling compatibility with MCUs having different I/O voltage domains. It also supports wired-OR reset bus configurations where multiple supervisors share a single reset line-critical in multi-processor or modular system designs.

How does the watchdog timer interact with the manual reset (MR) input?

The watchdog timer is cleared by any rising or falling edge on WDI, or by assertion of reset (RST high). When MR is pulled low, reset is asserted immediately and the watchdog timer stops counting. Upon MR release, reset remains active for trec (200 ms), after which the watchdog resumes timing-if no WDI toggle occurs within 1.6 s, it re-triggers reset. This ensures fail-safe recovery regardless of MR or WDI activity.