STMicroelectronics STM818LM6F
- Part No.:
- STM818LM6F
- Manufacturer:
- STMicroelectronics
- Category:
- Supervisors
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
STM818LM6F.pdf
- Description:
- IC SUPERVISOR 1 CHANNEL 8SO
- Quantity:
- Payment:

- Shipping:

Inventory:13,217
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Product details
Overview
STM818LM6F from STMicroelectronics is a 5 V microprocessor supervisory IC with integrated battery switchover, chip-enable gating, and dual active-low/high reset outputs. It monitors VCC for out-of-tolerance conditions (reset threshold = 4.63 V), asserts RST/RST for ≥200 ms (typ), and provides 7 ns max propagation delay for chip-enable control of external LPSRAM in industrial embedded systems.
For engineers reviewing the STM818LM6F datasheet, STM818LM6F pinout, STM818LM6F application, or STM818LM6F equivalent, this device is selected for non-volatile SRAM supervision where guaranteed reset assertion down to VCC = 1.0 V, low 0.4 µA battery supply current, and precise 1.6 sec watchdog timeout are critical design requirements.
Technical Context
The STM818LM6F implements a precision voltage reference and comparator to monitor VCC against a 4.63 V reset threshold with ±1.5% accuracy. Its internal watchdog timer triggers reset after 1.6 sec (typ) if WDI remains static, and it features push-pull RST/RST outputs guaranteed functional down to VCC = 1.0 V.
It integrates a P-channel MOSFET switchover switch (VCC ↔ VBAT) with 100 Ω on-resistance and supports chip-enable gating via E/ECON pins - a unique function among the STM8xx family enabling controlled LPSRAM access during reset or power transitions.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply voltage | 5 V nominal; operates across full industrial range (–40 °C to +85 °C) |
| Reset threshold | 4.63 V ±1.5%; ensures reliable MCU reset before brownout affects logic integrity |
| Reset timeout (trec) | 200 ms typical; guarantees minimum reset pulse width for proper processor initialization |
| Watchdog timeout | 1.6 sec typical; detects stalled firmware without requiring external timing components |
| Battery supply current | 0.4 µA typical; extends backup battery life in long-term storage or low-power modes |
| Chip-enable propagation delay | 7 ns maximum; enables high-speed LPSRAM gating without timing margin loss |
| VCC to VOUT on-resistance | 100 Ω typical; minimizes voltage drop during main supply operation |
Pinout & Package
STM818LM6F is housed in an 8-pin SO8 package (SOIC-8, 150 mil width) per STMicroelectronics mechanical specification DocID10522 Rev 11, Table 8.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1: RST | Active-high reset output | Push-pull output asserted high during reset; compatible with MCUs requiring active-high reset input |
| 2: VOUT | LPSRAM supply output | Switched output sourced from VCC or VBAT; powers external low-power SRAM during main supply failure |
| 3: PFO | Power-fail output | Push-pull output; not implemented on STM818 - pin is no-connect per datasheet Figure 6 and Table 3 |
| 4: ECON | Conditioned chip-enable output | Low only when E is low AND reset is de-asserted; enables gated LPSRAM access synchronized to system state |
| 5: E | Chip-enable input | Direct control input for LPSRAM gating; pulled low internally when unused |
| 6: MR | Manual reset input | Active-low input with internal pull-up; initiates reset on falling edge and holds for trec after release |
| 7: WDI | Watchdog input | Edge-sensitive input; toggling clears watchdog timer; floating disables watchdog function |
| 8: VCC | Main supply input | 5 V primary power rail; monitored for reset threshold violation and switchover control |
Key Features
| Feature | Design Value |
|---|---|
| Chip-enable gating | 7 ns max E-to-ECON propagation enables real-time LPSRAM access control without CPU intervention |
| Battery switchover | Automatic VCC/VBAT switching at lesser of VRST or VBAT ensures maximal battery runtime before switchover |
| Dual reset outputs | Simultaneous RST (active-low) and RST (active-high) support mixed-logic MCU platforms without level-shifting |
| Guaranteed reset down to 1.0 V | Ensures valid reset assertion even during deep VCC brownout, protecting SRAM data integrity |
| Battery freshness seal | Enables factory-sealed battery installation with zero standby drain until first VCC power-up |
Applications
| Industrial PLC Memory Backup | Medical Device Data Retention |
|---|---|
|
Use Scenario: Maintaining volatile configuration and calibration data in programmable logic controllers during AC mains interruption. IC Role / Device Role / Timing Role: Supervisory IC providing VCC monitoring, battery switchover to LPSRAM, and timed reset to ensure deterministic restart. Use Value: 0.4 µA battery current extends CR2032 life beyond 10 years; 200 ms trec meets IEC 61131-2 reset timing requirements. |
Use Scenario: Preserving patient therapy parameters and event logs in portable infusion pumps during battery replacement. IC Role / Device Role / Timing Role: Dual-reset supervisor with chip-enable gating ensures LPSRAM remains write-protected during power transition and reset assertion. Use Value: 7 ns E-to-ECON delay prevents LPSRAM access glitches; guaranteed 1.0 V reset assertion avoids corrupted parameter writes. |
| Smart Meter Firmware Recovery | Automotive Telematics SRAM Hold |
|
Use Scenario: Enabling safe firmware rollback and NVRAM recovery after unexpected power loss during OTA update. IC Role / Device Role / Timing Role: Watchdog-enabled supervisor detecting hung bootloader and triggering clean reset with battery-backed SRAM retention. Use Value: 1.6 sec watchdog timeout aligns with bootloader execution window; VBAT switchover preserves update state across power cycles. |
Use Scenario: Holding GPS position buffers and CAN message queues in vehicle infotainment units during ignition-off battery drain. IC Role / Device Role / Timing Role: Supervisor managing VCC/VBAT switchover and asserting RST/RST to coordinate MCU sleep/wake and SRAM gating. Use Value: Push-pull RST/RST outputs drive both legacy and modern MCU reset inputs; –40 °C to +85 °C rating meets AEC-Q100 ambient requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microprocessor supervisory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STM817LM6F | Lacks chip-enable gating (E/ECON); no PFI/PFO; includes battery freshness seal | Suitable for basic SRAM backup without gated access control; lower pin count required | Select when LPSRAM gating is unnecessary and cost optimization is prioritized over advanced control |
| STM805M6F | Single active-high RST output only; no watchdog, no battery switchover, no E/ECON | Designed for simple reset generation only; no memory supervision or backup functions | Select only for minimal reset-only use cases with no battery or SRAM interface requirements |
Compared with STM817LM6F and STM805M6F, the STM818LM6F uniquely delivers chip-enable gating for LPSRAM access control while retaining full battery switchover and watchdog functionality - making it the sole choice for designs requiring synchronized, glitch-free SRAM enablement during power transitions.
Availability
STM818LM6F is available at Aetrix Electronics and suitable for industrial PLC memory backup, medical device data retention, smart meter firmware recovery, and automotive telematics SRAM hold applications requiring stable component supply, long-lifecycle assurance, and RoHS-compliant packaging.
Supply support for STM818LM6F includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing analog, MCU, power, and sensing solutions for industrial, automotive, and consumer markets.
The STM8xx supervisor family targets robust, low-power memory supervision in mission-critical embedded systems - specifically engineered to simplify non-volatile SRAM interfacing with integrated switchover, reset, and watchdog functions.
FAQ
Is STM818LM6F pin-compatible with other STM8xx supervisors?
No. STM818LM6F uses a unique pinout: E (pin 5) and ECON (pin 4) replace PFI/PFO found on STM817/802/690A. Pin 3 (PFO) is no-connect on STM818, unlike functional PFO on STM817. Direct substitution requires PCB redesign and signal reassignment.
What is the function of the E and ECON pins?
E is a dedicated chip-enable input that controls LPSRAM access; ECON is its conditioned output, going low only when E is low AND reset is de-asserted. This prevents accidental LPSRAM writes during reset or power-up, ensuring data integrity during system initialization.
Does STM818LM6F support power-fail detection?
No. Unlike STM817/819, STM818LM6F omits PFI and PFO functionality entirely - confirmed by datasheet Figure 6 (pinout), Table 1 (device summary), and Section 2.8 ("NOT available on STM818"). Power-fail signaling must be implemented externally if required.
How does the battery freshness seal operate on STM818LM6F?
The battery freshness seal disables VBAT path leakage until first VCC power-up. When VCC rises above VRST (4.63 V), internal circuitry activates switchover logic - preventing battery drain during storage, shipping, or pre-deployment. Seal activation is automatic and requires no external command.
STM818LM6F Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- Simple Reset/Power-On Reset
- Number of Voltages Monitored:
- 1
- Voltage - Threshold:
- 4.65V
- Output:
- Push-Pull, Totem Pole
- Reset:
- Active Low
- Reset Timeout:
- 140ms Minimum
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
STM818LM6F FAQ
1.How can I place an order for STM818LM6F through Aetrix?
Please submit a Request for Quotation (RFQ) for STM818LM6F on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM818LM6F reliable?
The price and inventory of STM818LM6F are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM818LM6F is usually 5 days.
3.What payment methods are accepted for STM818LM6F?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM818LM6F transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM818LM6F?
STM818LM6F orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM818LM6F order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM818LM6F?
For technical support, including STM818LM6F datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM818LM6F requirements.
6.How does Aetrix verify that STM818LM6F is sourced from the original manufacturer or authorized distributors?
All STM818LM6F products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM818LM6F meets industry standards.
7.What is the process for return or replacement of STM818LM6F?
All STM818LM6F units undergo pre-shipment inspection (PSI). If there is an issue with STM818LM6F, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM818LM6F part is unused and in its original packaging.
Return procedure for STM818LM6F:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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MIC826SYMT-TR
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