STMicroelectronics STM818MM6E

Overview

STM818MM6E from STMicroelectronics is a 5 V microprocessor supervisor IC with integrated battery switchover, chip-enable gating, and dual reset outputs (RST and RST). It provides non-volatile RAM supervision for external LPSRAM, guarantees RST assertion down to VCC = 1.0 V, features 200 ms typical reset timeout (trec), and includes a 1.6 s watchdog timer. It is used in industrial embedded systems requiring reliable power monitoring and SRAM backup during main supply failure.

For engineers reviewing the STM818MM6E datasheet, STM818MM6E pinout, STM818MM6E application, or STM818MM6E equivalent, key selection criteria include chip-enable gating propagation delay (7 ns max), push-pull RST/RST outputs, battery switchover operation at VSO = min(VBAT, VRST), and absence of power-fail comparator (PFI/PFO) - distinguishing it from STM817/819 variants.

Technical Context

The STM818MM6E implements a precision voltage reference and comparator to monitor VCC against a fixed reset threshold (VRST ≈ 4.63 V), asserting RST low and RST high when VCC falls below VRST. Its internal watchdog timer triggers reset if WDI remains static for ≥1.6 s (typ), and is cleared on any WDI edge or during reset assertion.

It integrates a P-channel MOSFET-based battery switchover circuit that connects VOUT to VCC above VSO and to VBAT below VSO, with VSO dynamically set to the lesser of VBAT and VRST. The E-to-ECON chip-enable gating path operates with ≤7 ns propagation delay and conditional output control: ECON goes low only when E is low *and* reset is not asserted.

Key Specifications

Pinout & Package

STM818MM6E is housed in an 8-pin SO8 (Small Outline) package with standard 1.27 mm pitch, RoHS-compliant, lead-free construction per JEDEC MS-012.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar supervisor applications.

Compared with STM817MM6E and STM819MM6E, the STM818MM6E uniquely combines chip-enable gating and watchdog functionality - making it the only variant capable of both supervising MCU execution *and* synchronizing external LPSRAM access timing during reset transitions.

Availability

STM818MM6E is available at Aetrix Electronics and suitable for industrial data loggers, medical diagnostic devices, smart energy meters, and factory automation controllers requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.

Supply support for STM818MM6E includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing analog, microcontroller, power, and sensing solutions for industrial, automotive, and consumer markets.

The STM8xx supervisor family was developed specifically for robust, low-power microprocessor supervision in industrial embedded systems requiring battery-backed memory retention and deterministic reset behavior.

FAQ

Does STM818MM6E support power-fail detection (PFI/PFO)?

No. Unlike STM817MM6E and STM819MM6E, the STM818MM6E omits the power-fail comparator circuit. Pins PFI and PFO are not connected internally - PFO (Pin 3) is a no-connect. This omission enables dedicated silicon area for the E/ECON chip-enable gating function, confirmed in Figure 3 and Table 3 of the official datasheet (DocID10522 Rev 11).

What is the function of the E and ECON pins?

E is a logic input that enables the chip-enable gating path; ECON is its conditioned output. ECON goes low only when E is low *and* reset is not asserted - preventing LPSRAM access during reset. The path has ≤7 ns propagation delay (typ), allowing precise timing alignment with MCU operation, as detailed in Section 2.5 and Figure 11 of the datasheet.

Can STM818MM6E operate without a backup battery?

Yes. When no battery is used, connect VBAT to VCC per datasheet recommendation (Section 1.1.6). The device functions fully as a 5 V supervisor with watchdog and dual reset outputs. Battery switchover is disabled, but all other features - including E/ECON gating and RST timing - remain operational and specified down to VCC = 1.0 V.

How is the reset timeout (trec) determined?

trec is a fixed internal timer value of 200 ms (typical), not adjustable externally. It begins counting when VCC rises above VRST (4.63 V), holds RST low for the full duration, then releases reset. This timing is guaranteed over temperature and supply voltage, and applies identically to assertions triggered by VCC drop, MR activation, or watchdog timeout - as specified in Section 2.1 and Table 7.