STMicroelectronics STMLS05ACQTR
- Part No.:
- STMLS05ACQTR
- Manufacturer:
- STMicroelectronics
- Package:
- 16-UFQFN
- Datasheet:
-
STMLS05ACQTR.pdf
- Description:
- IC SW SPSTX5 125MOHM 16UFQFPN
- Quantity:
- Payment:

- Shipping:

Inventory:2,787
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Product details
Overview
STMLS05ACQTR from STMicroelectronics is a five-channel PMOS load switch array with I²C programmability, soft-start timing control (1/2/4/8 ms), individual channel enable/disable, and ultra-low quiescent current (2.4 µA max). It operates across 1.05–5.5 V input/output and 1.8–3.6 V VDD, delivering up to 100 mA per channel with 120 mΩ typical RON at 1.8 V. Used in smartphone power rail sequencing and wearable device peripheral management.
For engineers reviewing the STMLS05ACQTR datasheet, STMLS05ACQTR pinout, STMLS05ACQTR application, or STMLS05ACQTR equivalent, key selection criteria include per-channel soft-start programmability, output discharge control, EN_SW0 hardware override for Channel 0, UVLO-protected VDD startup, and UFQFPN-16 package compatibility with high-density mobile PCB layouts.
Technical Context
The device integrates five independent PMOS high-side switches with dedicated output discharge circuitry per channel, activated on turn-off with configurable duration (1.7–8.3 ms) or permanent mode. Each switch features programmable soft-start via I²C register bits ST2_x/ST1_x/ST0_x to limit inrush current during power-up.
Control is dual-mode: full I²C register access (base address 0x5C) for all five channels plus hardware pins EN_SW0 (Channel 0 override) and EN_I2C (I²C block disable). The VDD UVLO circuit (1.35 V typ.) forces all switches and registers into reset state if supply drops below threshold, ensuring robust power sequencing.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Channels | 5 independent PMOS high-side load switches |
| VIN/VOUT Range | 1.05 V to 5.5 V - supports wide-input mobile rails including 1.2 V, 1.8 V, 3.3 V, and 5 V peripherals |
| VDD Supply | 1.8 V to 3.6 V - powers internal logic and I²C interface only; decoupled from load voltage domain |
| Max Output Current | 100 mA per channel - sufficient for low-power sensors, LEDs, and RF modules without thermal derating |
| RON (typ) | 120 mΩ at 1.8 V - enables <120 mV drop at 100 mA, minimizing power loss and heat generation |
| Quiescent Current | 2.4 µA max - ensures negligible battery drain in always-on system standby states |
| Soft-Start Options | 1 / 2 / 4 / 8 ms - prevents >1 A inrush into 47 µF capacitive loads common in display and audio subsystems |
Pinout & Package
Package: UFQFPN, 3 × 3 mm, 16-lead, exposed pad (ECOPACK® compliant, lead-free/halogen-free).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1–4, 16 | VIN0–VIN4 | Independent input power rails for each channel; accepts 1.05–5.5 V, electrically isolated |
| 5 | GND | Common ground reference for logic and power domains; connects to exposed thermal pad |
| 6, 7 | SCL, SDA | I²C bus interface - supports standard-mode (400 kHz) with 0.6 µs hold/setup timing |
| 8 | EN_SW0 | Hardware enable for Channel 0 only - overrides I²C EN_0 bit; active-high, VDD-referenced |
| 9–13 | OUT4–OUT0 | Switched outputs - each drives downstream load with integrated discharge path when disabled |
| 14 | EN_I2C | Global I²C block enable - disables register access while preserving last switch states |
| 15 | VDD | Dedicated 1.8–3.6 V supply for internal logic, I²C, and UVLO circuit - not connected to VIN rails |
Key Features
| Feature | Design Value |
|---|---|
| Per-channel soft-start programming | I²C-configurable 1/2/4/8 ms ramp prevents inrush-induced voltage droop on shared power rails |
| Output discharge control | Configurable discharge pulse (1.7–8.3 ms) or permanent discharge eliminates floating outputs and ESD risk |
| VDD UVLO protection | 1.35 V threshold resets all switches and registers during brown-out, preventing undefined behavior |
| Hardware override for Channel 0 | EN_SW0 pin allows boot-time or safety-critical activation of primary load independent of I²C firmware |
| Ultra-low static power | 2.4 µA max IDD(OFF) extends battery life in always-on wearables and IoT edge nodes |
Applications
| Smartphone Power Sequencing | Tablet Peripheral Management |
|---|---|
Use Scenario: Sequential enabling of camera module, fingerprint sensor, and NFC transceiver during boot. IC Role / Device Role / Timing Role: Five-channel high-side switch providing controlled, staggered power delivery with soft-start to avoid system-wide voltage sag. Use Value: Prevents >1 A inrush into 47 µF camera rail capacitance, maintaining stable 3.3 V core voltage during initialization. | Use Scenario: Dynamic power gating of USB-C accessory detection circuitry and stylus charging interface. IC Role / Device Role / Timing Role: I²C-programmable load switch enabling/disabling peripheral rails based on accessory presence detection. Use Value: Reduces standby current by 2.4 µA per inactive channel, extending tablet battery runtime by >12 hours in sleep mode. |
| Wearable Sensor Hub | Mobile Audio Subsystem |
Use Scenario: Isolating accelerometer, gyroscope, and heart-rate monitor from main SoC power domain. IC Role / Device Role / Timing Role: Independent channel control with EN_SW0 hardware override for emergency sensor wake-up. Use Value: Enables sub-100 µA deep-sleep current by fully disconnecting sensor VDD while retaining I²C accessibility. | Use Scenario: Powering headphone amplifier, DAC, and MEMS microphone bias circuits on demand. IC Role / Device Role / Timing Role: Soft-started load switching prevents audible pop/click during audio playback start-up. Use Value: 1 ms soft-start eliminates transient coupling into analog audio paths, meeting -80 dB THD+N requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar multi-channel load switch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPL7407LDR | 7-channel N-channel sink driver; requires external pull-up; no soft-start or discharge | Designed for logic-level sinking (e.g., LED arrays), not high-side power rail switching | Select only for low-voltage digital signal driving where sourcing capability and soft-start are unnecessary |
| TPS22965DSGT | Single-channel 5.5 V, 2 A load switch; 35 mΩ RON; no I²C; fixed 1.5 ms soft-start | Lacks multi-channel integration and per-channel programmability; higher current rating overshoots typical mobile peripheral needs | Choose when single-rail control suffices and board space permits discrete switches per load |
Compared with TPL7407LDR and TPS22965DSGT, STMLS05ACQTR uniquely delivers five independently programmable high-side switches in one 3×3 mm package, combining soft-start, discharge, UVLO, and hardware override - essential for compact, battery-sensitive mobile power architectures.
Availability
STMLS05ACQTR is available at Aetrix Electronics and suitable for smartphone power sequencing, tablet peripheral management, wearable sensor hub control, and mobile audio subsystems requiring stable component supply across extended production lifecycles.
Supply support for STMLS05ACQTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, sensors, and analog devices for automotive, industrial, and consumer markets.
The STMLS05 belongs to ST's enhanced load switch product line, engineered specifically for space-constrained mobile platforms requiring precise, low-power, multi-rail power control with robust sequencing and protection features.
FAQ
What is the function of the EN_I2C pin?
The EN_I2C pin globally disables the I²C interface while preserving the last known state of all five load switches. When pulled low, it ignores incoming I²C commands but maintains channel ON/OFF status. This allows firmware-independent power control during critical boot phases or fault recovery sequences without disrupting active loads.
Can Channel 0 be controlled both by I²C and the EN_SW0 pin simultaneously?
Yes - Channel 0 activation is the logical OR of the EN_0 bit (I²C register 0x05) and the EN_SW0 pin. If either is asserted, the channel turns ON. This dual-control architecture enables firmware-based sequencing while retaining hardware-level fail-safe activation, such as forcing camera power during emergency boot.
How does the VDD UVLO circuit affect system reliability?
The VDD UVLO (1.35 V threshold) forces all switches OFF and resets internal registers when supply drops below specification. This prevents partial or undefined operation during brown-out conditions, eliminating risk of latch-up, data corruption in I²C registers, or uncontrolled discharge into downstream circuitry - critical for certified mobile device safety compliance.
Is the output discharge feature mandatory or configurable per channel?
Discharge is fully configurable per channel via I²C register bits DEx (enable) and DTx (type). Setting DEx = 0 disables discharge entirely; DEx = 1 + DTx = 0 enables timed discharge (1.7–8.3 ms); DEx = 1 + DTx = 1 enables permanent discharge until re-enabled. No external components are required for any mode.
STMLS05ACQTR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Switch Circuit:
- SPST
- Multiplexer/Demultiplexer Circuit:
- 1:1
- Number of Circuits:
- 5
- On-State Resistance (Max):
- 125mOhm
- Channel-to-Channel Matching (ΔRon):
- -
- Voltage - Supply, Single (V+):
- 1.8V ~ 3.6V
- Voltage - Supply, Dual (V±):
- -
- Switch Time (Ton, Toff) (Max):
- 10ms, 1.7ms
- -3db Bandwidth:
- -
- Charge Injection:
- -
- Channel Capacitance (CS(off), CD(off)):
- -
- Current - Leakage (IS(off)) (Max):
- 200nA
- Crosstalk:
- -
- Operating Temperature:
- -40°C ~ 70°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-UFQFPN (3x3)
STMLS05ACQTR FAQ
1.How can I place an order for STMLS05ACQTR through Aetrix?
Please submit a Request for Quotation (RFQ) for STMLS05ACQTR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STMLS05ACQTR reliable?
The price and inventory of STMLS05ACQTR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STMLS05ACQTR is usually 5 days.
3.What payment methods are accepted for STMLS05ACQTR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STMLS05ACQTR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STMLS05ACQTR?
STMLS05ACQTR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STMLS05ACQTR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STMLS05ACQTR?
For technical support, including STMLS05ACQTR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STMLS05ACQTR requirements.
6.How does Aetrix verify that STMLS05ACQTR is sourced from the original manufacturer or authorized distributors?
All STMLS05ACQTR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STMLS05ACQTR meets industry standards.
7.What is the process for return or replacement of STMLS05ACQTR?
All STMLS05ACQTR units undergo pre-shipment inspection (PSI). If there is an issue with STMLS05ACQTR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STMLS05ACQTR part is unused and in its original packaging.
Return procedure for STMLS05ACQTR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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