STMicroelectronics STV8164

Overview

STV8164 from STMicroelectronics is a monolithic triple positive voltage regulator IC providing two fixed 5 V ±2% outputs (each rated ≥0.6 A) and one adjustable output (2.5–16 V ±2%, ≥0.6 A), with integrated reset (triggered at VOUT1–0.25 V) and digital disable (pins 10 & 11) functions. It operates from 7–18 V input, features short-circuit and thermal shutdown protection, and is used in multi-rail consumer and industrial power supplies requiring coordinated sequencing and fault monitoring.

For engineers reviewing the STV8164 datasheet, STV8164 pinout, STV8164 application, or STV8164 equivalent, key selection considerations include its triple-output regulation architecture, reset threshold hysteresis (30–120 mV), dropout voltage (1.0–1.4 V at 0.6 A), disable logic levels (V_DISL ≤ 0.8 V, V_DISH ≥ 2 V), and thermal shutdown at 150 °C with 15 °C hysteresis.

Technical Context

The STV8164 integrates three independent linear regulators sharing a single trimmed zener reference supplied via INPUT1; thus OUTPUT2 and OUTPUT3 are inactive if INPUT1 is unpowered. Each output uses a Darlington pass stage, delivering low dropout (1.0 V typ.) and high short-circuit current capability (0.8–1.8 A).

Its reset function monitors OUTPUT1 voltage with dual-comparator hysteresis: comparator "a" triggers immediate low-going RESET when VOUT1 falls below K−0.25 V, while comparator "b" provides noise immunity via 1.9 V hysteresis. The external delay capacitor (pin 4) sets t_RD = 25 ms (with C_e = 100 nF), and the PROGRAM pin (pin 9) sets OUTPUT3 via resistor divider feedback to maintain 2.0 V at that node.

Key Specifications

Pinout & Package

STV8164 is housed in an 11-pin Clipwatt plastic package (SO-11 variant), with exposed heat slug for thermal management. Pin pitch is 2.54 mm, body width 17.9 mm, and maximum height 19.85 mm.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar triple-voltage regulator applications.

Compared with LM2596S-5.0 and TPS7A4700RGWR, the STV8164 uniquely integrates dual precision 5 V rails, programmable third rail, reset generation, and digital disable in one monolithic device-reducing component count, layout complexity, and startup coordination overhead in multi-rail systems.

Availability

STV8164 is available at Aetrix Electronics and suitable for set-top box power management, industrial PLC I/O modules, legacy CRT monitor auxiliary supplies, and medical diagnostic imaging subsystems requiring stable component supply and long-term obsolescence mitigation.

Supply support for STV8164 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing analog, microcontroller, power, and sensor solutions for automotive, industrial, and consumer markets.

The STV8164 belongs to ST's legacy linear regulator product line, engineered specifically for cost-sensitive, space-constrained multi-rail power systems where integration of reset supervision and digital enable/disable simplifies board-level power architecture.

FAQ

What is the minimum input voltage required for stable operation of all three outputs?

The STV8164 requires minimum input voltages of 7 V on INPUT1, INPUT2, and INPUT3. INPUT1 must be powered first, as it supplies the shared reference; if INPUT1 is below 7 V, OUTPUT2 and OUTPUT3 will not regulate regardless of their respective input voltages. Dropout is 1.0 V typical, so 6 V on INPUT1 would cause OUTPUT1 to drop out.

How is the reset delay time determined, and can it be adjusted?

The reset delay time (t_RD) is set by an external capacitor connected to pin 4 (DELAY CAPACITOR). With C_e = 100 nF, t_RD = 25 ms. Increasing capacitance linearly increases delay; decreasing it reduces delay. The internal 10 µA current source charges the capacitor to 2.5 V, defining the timing constant. No resistor is needed-only the capacitor.

Can OUTPUT2 and OUTPUT3 be disabled independently?

No-OUTPUT2 and OUTPUT3 share a single digital disable control via pin 10 (DISABLE). When DISABLE is pulled below 0.8 V, both outputs shut down simultaneously. There is no provision for independent enable/disable control; they function as a pair. This simplifies control logic but requires external switching if independent rail control is needed.

What thermal derating guidance applies when using all three outputs at full current?

With all outputs delivering 0.6 A, total power dissipation can exceed safe limits. At T_AMB = 70 °C and R_thJA = 12 °C/W, max allowable dissipation is 5.8 W. For example, with VIN1 = VIN2 = 12 V and VOUT3 = 12 V, the sum (VIN1−5)×0.6 + (VIN2−5)×0.6 + (VIN3−12)×0.6 must stay below 5.8 W. Derate output currents or add heatsinking if ambient exceeds 50 °C.