Microchip Technology SY87700LHG-TR

Overview

SY87700LHG-TR from Micrel is a 3.3V clock and data recovery (CDR) IC supporting NRZ data rates from 32 Mbps to 175 Mbps, featuring dual on-chip PLLs for independent clock generation and recovery, differential PECL I/O, and link fault detection. It operates across –40°C to +85°C and targets SONET/SDH OC-1/OC-3 and ATM systems.

For engineers reviewing the SY87700LHG-TR datasheet, SY87700LHG-TR pinout, SY87700LHG-TR application, or SY87700LHG-TR equivalent, key selection criteria include its 32–175 Mbps AnyRate® CDR capability, dual-PLL architecture with selectable reference frequencies, PECL-compatible serial I/O, and compliance with GR-253-CORE and G.958 jitter specifications.

Technical Context

The SY87700LHG-TR implements two independent PLLs: one for clock recovery (phase/frequency detector + VCO + loop filter pins PLLRP/PLLRN) and another for clock synthesis (PLLSN/PLLSP). The recovered clock (RCLKP/RCLKN) and transmit clock (TCLKP/TCLKN) are both differential PECL outputs with ≤0.01 UI rms jitter generation and >1000 ppm frequency lock tolerance.

It supports five user-selectable data rate ranges via FREQSEL1–3 (e.g., 125–175 Mbps at 6× VCO ratio), and REFCLK-based fallback during loss-of-signal. Link fault indication (LFIN) is TTL-level and asynchronous, asserting HIGH when the receiver PLL achieves lock within ±1000 ppm of the incoming data rate.

Key Specifications

Pinout & Package

SY87700LHG-TR is packaged in a 32-pin EPAD-TQFP (H32-1) with exposed thermal pad for enhanced heat dissipation (θJA = 20.7°C/W at 500 lfpm airflow). The package supports Pb-free NiPdAu finish and is recommended for new designs over the obsolete 28-pin SOIC variant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock and data recovery applications.

Compared with SY87700LHG-TR, the SY87700ALHG-TR offers identical functionality at lower ICC (170 mA), making it the preferred drop-in replacement for new designs, while the ICS87200AGI-01LF provides cost-effective retiming but omits the clock synthesis PLL and selectable TCLK sourcing - limiting use in multi-clock-domain architectures.

Availability

SY87700LHG-TR is available at Aetrix Electronics and suitable for SONET/SDH line cards, ATM edge switches, and broadcast video transport systems requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SY87700LHG-TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Micrel, Inc. was a U.S.-based analog and mixed-signal semiconductor company acquired by Microchip Technology in 2015; known for high-performance timing, power management, and interface ICs.

The SY87700LHG-TR belongs to Micrel's AnyRate® CDR product line, engineered specifically for carrier-grade SONET/SDH, ATM, and broadcast video applications demanding low-jitter, multi-rate clock recovery in industrial temperature environments.

FAQ

What is the operating temperature range for the SY87700LHG-TR?

The SY87700LHG-TR is rated for industrial temperature operation from –40°C to +85°C. This range is validated across all electrical specifications including jitter performance, lock acquisition time, and DC parameters. The 32-pin EPAD-TQFP package's thermal resistance (20.7°C/W at 500 lfpm) ensures reliable operation under sustained load within this ambient envelope. SY87700LHG-TR maintains full compliance with GR-253-CORE jitter specs across the entire range.

Does the SY87700LHG-TR require external loop filter components?

Yes, the SY87700LHG-TR requires external passive components on both PLL loop filter pins: PLLRP/PLLRN for the recovery PLL and PLLSP/PLLSN for the synthesis PLL. Recommended values are R5 = 350 Ω and C3 = 1.0 µF (X7R) for recovery, and R6 = 680 Ω and C4 = 1.0 µF (X7R) for synthesis. These networks set loop bandwidth and stability; omitting them prevents PLL lock. SY87700LHG-TR will not function correctly without properly configured external filters.

Can the SY87700LHG-TR be used in place of the SY87700LZI or SY87700LHI variants?

Yes, the SY87700LHG-TR is functionally identical to SY87700LZI and SY87700LHI but differs in packaging and finish: SY87700LHG-TR uses Pb-free NiPdAu-finished 32-pin EPAD-TQFP (H32-1), whereas SY87700LZI uses Sn-Pb 28-pin SOIC and SY87700LHI uses Sn-Pb 32-pin EPAD-TQFP. The SY87700LHG-TR replaces both for new designs per Micrel's guidance, offering superior thermal performance and RoHS compliance. Pinout and electrical behavior of SY87700LHG-TR match SY87700LHI exactly.

What is the purpose of the CD (Carrier Detect) input on the SY87700LHG-TR?

The CD input on the SY87700LHG-TR controls whether the receiver PLL actively tracks the RDIN data stream. When CD = HIGH, normal clock recovery occurs; when CD = LOW, SY87700LHG-TR forces RDOUT to LOW, disables data recovery, and locks the PLL to REFCLK. This prevents false lock during idle periods and enables deterministic failover in optical link monitoring circuits. CD is a PECL-level input compatible with standard optical module carrier detect outputs.

How does the SY87700LHG-TR handle loss-of-signal conditions?

During loss-of-signal, the SY87700LHG-TR uses the REFCLK input as a fallback reference: the receiver PLL locks to REFCLK frequency, maintaining stable RCLK/TCLK outputs while asserting LFIN LOW. If CD remains HIGH but RDIN deviates >±1000 ppm from expected rate, SY87700LHG-TR declares loss of lock and reverts to REFCLK-based operation. Recovery is automatic upon valid RDIN return - no reset or configuration change is needed. This behavior is fully specified in the functional description and verified across temperature.