Microchip Technology TC1303B-1P0EMFTR
- Part No.:
- TC1303B-1P0EMFTR
- Manufacturer:
- Microchip Technology
- Category:
- Voltage Regulators - Linear + Switching
- Package:
- 10-VFDFN Exposed Pad
- Datasheet:
-
TC1303B-1P0EMFTR.pdf
- Description:
- IC REG DL BUCK/LINEAR SYNC 10DFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
TC1303B-1P0EMFTR from Microchip Technology is a dual-output power management IC integrating a 500 mA synchronous buck regulator and a 300 mA low-dropout linear regulator (LDO), with power-good monitoring specifically of the LDO output. It delivers fixed 1.0 V on VOUT1 (buck) and fixed 3.3 V on VOUT2 (LDO), operates from 2.7–5.5 V input, achieves >90% peak efficiency at 2.0 MHz switching frequency, and supports -40°C to +125°C junction temperature - ideal for portable medical instruments requiring stable dual-rail biasing.
For engineers reviewing the TC1303B-1P0EMFTR datasheet, TC1303B-1P0EMFTR pinout, TC1303B-1P0EMFTR application, or TC1303B-1P0EMFTR equivalent, key selection criteria include its LDO-monitored PG signal, independent shutdown control per rail, 65 µA typical quiescent current, 137 mV typical dropout at 200 mA, and 10-pin DFN (3×3 mm) package compatibility with space-constrained USB-powered devices.
Technical Context
The TC1303B-1P0EMFTR implements a fixed-frequency 2.0 MHz PWM buck stage with automatic transition to PFM mode under light load to minimize IQ, while its LDO uses internal compensation and requires only a single 1 µF ceramic output capacitor. Its power-good output is a push-pull signal asserted when VOUT2 reaches ≥94% of regulation, with 300 ms delay for processor reset sequencing.
Both regulators feature undervoltage lockout (UVLO at 2.55 V nominal), overtemperature protection (165°C trip), and short-circuit protection. The buck stage integrates P- and N-channel MOSFETs with 450 mΩ typical RDS(on), and the LDO maintains ±0.3% output voltage tolerance across load and temperature.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VOUT1 (Buck) | Fixed 1.0 V output; enables low-voltage core supply for microcontrollers or FPGAs with tight regulation (±0.3%) |
| VOUT2 (LDO) | Fixed 3.3 V output; powers I/O interfaces or sensors with 137 mV dropout at 200 mA, minimizing input headroom |
| Switching Frequency | 2.0 MHz (typical); allows use of small 4.7 µH inductor and 4.7 µF output capacitor for compact layout |
| Quiescent Current | 65 µA (typical, both rails active); extends battery life in always-on portable applications |
| Power-Good Output | Push-pull PG referenced to VOUT2; asserts after 300 ms delay once VOUT2 reaches 94% of 3.3 V, directly driving processor RESET |
| Operating Temp | -40°C to +125°C junction range; qualified for industrial and medical environments without derating |
| Package | 10-pin 3×3 mm DFN; exposed pad tied to AGND for thermal performance (θJA = 41°C/W) |
Pinout & Package
TC1303B-1P0EMFTR is housed in a 10-pin 3×3 mm DFN package with exposed thermal pad (EP) connected to AGND. Pin 1 is SHDN2 (active-high LDO enable), Pin 2 is VIN2 (LDO input), Pin 3 is VOUT2 (3.3 V LDO output), Pin 4 is PG (push-pull power-good), Pin 5 is AGND (analog ground), Pin 6 is PGND (power ground), Pin 7 is LX (buck switch node), Pin 8 is VIN1 (buck input), Pin 9 is SHDN1 (active-high buck enable), and Pin 10 is VFB1/VOUT1 (1.0 V buck output).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| SHDN2 (Pin 1) | LDO enable input | Logic-high (>45% VIN) activates 3.3 V LDO; independent of buck rail for flexible power sequencing |
| VIN2 (Pin 2) | LDO input supply | Accepts 2.7–5.5 V; must be routed adjacent to VIN1 with minimal trace length to reduce noise coupling |
| VOUT2 (Pin 3) | LDO regulated output | Delivers 3.3 V @ 300 mA; requires ≥1 µF ceramic capacitor to AGND for stability |
| PG (Pin 4) | Power-good status output | Push-pull signal high when VOUT2 ≥3.102 V; drives RESET directly without external pull-up |
| AGND (Pin 5) | Analog reference ground | Must connect to quiet analog ground plane; separate from PGND except at single-point star connection |
| PGND (Pin 6) | Power ground return | Carries high di/dt buck switching current; connects to thermal pad and input/output capacitors |
| LX (Pin 7) | Buck switch node | Connects to inductor and catch diode; requires tight loop area with VIN1 and PGND to minimize EMI |
| VIN1 (Pin 8) | Buck input supply | Shares input source with VIN2; UVLO ensures both rails disable below 2.55 V |
| SHDN1 (Pin 9) | Buck enable input | Logic-high (>45% VIN) activates 1.0 V buck; allows independent rail control for low-power sleep modes |
| VFB1/VOUT1 (Pin 10) | Buck output / feedback | Provides 1.0 V fixed output; no external divider needed - simplifies layout and reduces BOM count |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent shutdown | SHDN1 and SHDN2 allow staggered enable/disable of buck and LDO rails - critical for low-power state transitions in handheld devices |
| LDO-monitored power-good | PG asserts only when VOUT2 reaches regulation, ensuring reliable reset timing for 3.3 V–dependent peripherals before system boot |
| Internally compensated LDO | Eliminates need for external compensation network; 1 µF ceramic output capacitor suffices for full 300 mA load stability |
| 2.0 MHz fixed-frequency PWM | Enables use of miniature 4.7 µH shielded inductors and reduces output ripple vs. lower-frequency alternatives |
| Automatic PWM-to-PFM mode transition | Maintains high efficiency down to µA-level loads without manual mode control or external circuitry |
| Thermal and short-circuit protection | 165°C thermal shutdown with 10°C hysteresis and cycle-by-cycle current limiting prevent damage during fault conditions |
Applications
| Portable Medical Sensors | USB-Powered Test Equipment |
|---|---|
Use Scenario: Battery-operated glucose meter with MCU core (1.0 V) and LCD interface (3.3 V). IC Role / Device Role / Timing Role: TC1303B-1P0EMFTR supplies both rails; PG output triggers MCU reset after LDO stabilizes. Use Value: 65 µA quiescent current extends AA battery life beyond 12 months in standby; 137 mV LDO dropout enables operation down to 3.43 V input. | Use Scenario: Handheld oscilloscope powered via USB 5 V, requiring clean 1.0 V FPGA core and 3.3 V ADC reference. IC Role / Device Role / Timing Role: TC1303B-1P0EMFTR generates isolated, low-noise rails; buck's 2.0 MHz switching avoids interference with 100 kHz–10 MHz measurement bandwidth. Use Value: Internally compensated LDO eliminates external components; push-pull PG drives scope's FPGA reset without pull-up resistor. |
| Industrial Handheld Terminals | Low-Power IoT Edge Nodes |
Use Scenario: Rugged barcode scanner with ARM Cortex-M core (1.0 V) and RS-232 transceiver (3.3 V), operating from 3.6 V Li-ion. IC Role / Device Role / Timing Role: TC1303B-1P0EMFTR provides regulated dual outputs; independent SHDN pins allow deep-sleep mode where only LDO remains active. Use Value: -40°C to +125°C rating ensures reliability in warehouse environments; 450 mΩ RDS(on) MOSFETs limit conduction loss at 500 mA buck load. | Use Scenario: Wireless sensor node using BLE SoC (1.0 V core) and environmental sensor (3.3 V I²C interface), powered by coin cell. IC Role / Device Role / Timing Role: TC1303B-1P0EMFTR delivers precise rails; automatic PFM mode reduces IQ to <10 µA during 99% sleep duty cycle. Use Value: 1.0 V buck output matches SoC core voltage exactly - avoiding inefficient post-regulation; PG signal validates LDO before BLE radio wake-up. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-output PMIC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TC1303B-1P0EUNTR | Identical electrical specs and pinout; differs only in MSOP-10 package (5×4.4 mm) vs. DFN-10 (3×3 mm) | Requires PCB redesign for larger footprint and different thermal pad layout; less suitable for ultra-compact designs | Select when board space permits larger package and MSOP soldering process is preferred |
| TPS65023BRSBR | Triple-output (2 buck + 1 LDO); higher IQ (100 µA); no LDO-specific PG - monitors buck1 only | Supports more complex SoC power trees but lacks TC1303B-1P0EMFTR's LDO-targeted reset timing | Choose when additional voltage rails are required and LDO-monitored reset is not critical |
Compared with TC1303B-1P0EUNTR, the TC1303B-1P0EMFTR saves 55% board area and improves thermal resistance by 72°C/W; versus TPS65023BRSBR, it offers tighter LDO regulation control and lower quiescent current but fewer output channels.
Availability
TC1303B-1P0EMFTR is available at Aetrix Electronics and suitable for portable medical instruments, USB-powered test equipment, and industrial handheld terminals requiring stable dual-rail component supply with guaranteed long-term availability.
Supply support for TC1303B-1P0EMFTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a leading provider of microcontroller, analog, and Flash-IP solutions, serving automotive, industrial, consumer, and communications markets with high-reliability silicon and development tools.
The TC1303 family targets space- and power-constrained portable electronics, delivering integrated dual-rail power conversion with minimal external components and robust protection features for battery-operated systems.
FAQ
What is the exact output voltage configuration of TC1303B-1P0EMFTR?
The TC1303B-1P0EMFTR is factory-configured with a fixed 1.0 V output on VOUT1 (buck regulator) and a fixed 3.3 V output on VOUT2 (LDO). This is encoded in the part number suffix "1P0" (1.0 V buck) and "EMF" (3.3 V LDO), per Microchip's TC1303B ordering guide. No external feedback resistors are required.
How does the power-good (PG) function behave on TC1303B-1P0EMFTR?
The TC1303B-1P0EMFTR's PG pin is a push-pull output that monitors only the LDO (VOUT2) rail. It asserts high when VOUT2 reaches ≥94% of 3.3 V (≥3.102 V) and holds for ≥262 ms minimum. The 300 ms delay is implemented internally and is used directly for processor reset timing - no external RC network is needed.
Can TC1303B-1P0EMFTR operate with separate input sources for VIN1 and VIN2?
No - the TC1303B-1P0EMFTR datasheet explicitly states in Note 8 that VIN1 and VIN2 "are supplied by the same input source." Routing separate supplies violates the internal UVLO and current-sharing design, and may cause startup failure or undefined behavior. Both inputs must be shorted together on the PCB.
What is the recommended output capacitance for VOUT2 on TC1303B-1P0EMFTR?
TC1303B-1P0EMFTR requires a minimum 1.0 µF ceramic capacitor between VOUT2 and AGND, as specified in the Typical Application Circuits (DS21949C-page 5). Microchip validates stability with X5R/X7R dielectrics; larger values (e.g., 2.2 µF) improve transient response but are not required for basic operation.
Does TC1303B-1P0EMFTR support automatic power sequencing between its two outputs?
No - automatic sequencing is exclusive to the TC1304 variant. The TC1303B-1P0EMFTR provides independent SHDN1 (buck) and SHDN2 (LDO) inputs, enabling manual sequencing via controller GPIOs, but contains no internal sequencer. Startup order depends entirely on external timing of the two enable signals.
TC1303B-1P0EMFTR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 10-VFDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Topology:
- Step-Down (Buck) Synchronous (1), Linear (LDO) (1)
- Number of Outputs:
- 2
- Frequency - Switching:
- 2MHz
- Voltage/Current - Output 1:
- 1.375V, 500mA
- Voltage/Current - Output 2:
- 1.8V, 300mA
- Voltage/Current - Output 3:
- -
- w/LED Driver:
- No
- w/Supervisor:
- No
- w/Sequencer:
- Yes
- Voltage - Supply:
- 2.7V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 10-DFN (3x3)
TC1303B-1P0EMFTR FAQ
1.How can I place an order for TC1303B-1P0EMFTR through Aetrix?
Please submit a Request for Quotation (RFQ) for TC1303B-1P0EMFTR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TC1303B-1P0EMFTR reliable?
The price and inventory of TC1303B-1P0EMFTR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TC1303B-1P0EMFTR is usually 5 days.
3.What payment methods are accepted for TC1303B-1P0EMFTR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TC1303B-1P0EMFTR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TC1303B-1P0EMFTR?
TC1303B-1P0EMFTR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TC1303B-1P0EMFTR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TC1303B-1P0EMFTR?
For technical support, including TC1303B-1P0EMFTR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TC1303B-1P0EMFTR requirements.
6.How does Aetrix verify that TC1303B-1P0EMFTR is sourced from the original manufacturer or authorized distributors?
All TC1303B-1P0EMFTR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TC1303B-1P0EMFTR meets industry standards.
7.What is the process for return or replacement of TC1303B-1P0EMFTR?
All TC1303B-1P0EMFTR units undergo pre-shipment inspection (PSI). If there is an issue with TC1303B-1P0EMFTR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TC1303B-1P0EMFTR part is unused and in its original packaging.
Return procedure for TC1303B-1P0EMFTR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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