My Inquiry
My Account
Microchip Technology TC1303B-PA0EUNTR
- Part No.:
- TC1303B-PA0EUNTR
- Manufacturer:
- Microchip Technology
- Category:
- Voltage Regulators - Linear + Switching
- Package:
- 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
- Datasheet:
-
TC1303B-PA0EUNTR.pdf
- Description:
- IC REG DL BUCK/LNR SYNC 10MSOP
- Quantity:
- Payment:
- Shipping:
Inventory:4,569
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
TC1303B-PA0EUNTR from Microchip Technology is a dual-output power management IC integrating a 500 mA synchronous buck regulator and a 300 mA low-dropout linear regulator (LDO), with the power-good (PG) signal monitoring only the LDO output (VOUT2). It delivers 1.8 V at 500 mA and 3.3 V at 300 mA from a 2.7–5.5 V input, features 65 µA typical quiescent current, 2.0 MHz fixed-frequency PWM operation, and operates across –40°C to +125°C junction temperature. It targets portable battery-powered systems requiring tightly regulated dual rails.
For engineers reviewing the TC1303B-PA0EUNTR datasheet, TC1303B-PA0EUNTR pinout, TC1303B-PA0EUNTR application, or TC1303B-PA0EUNTR equivalent, key selection criteria include LDO-monitored PG behavior, independent SHDN2 control for the LDO, 137 mV typical dropout at 200 mA, internal compensation, and DFN/MSOP package compatibility with thermal pad grounding.
Technical Context
The TC1303B-PA0EUNTR implements a fixed-frequency 2.0 MHz synchronous buck converter with automatic transition to PFM mode under light load to maintain ultra-low IQ, while its LDO uses a separate input (VIN2) and provides rail-specific regulation with 0.3% output tolerance. The PG pin is push-pull and asserts when VOUT2 reaches ≥94% of nominal, with 300 ms delay-designed explicitly for processor reset timing in embedded applications.
Unlike TC1303A (buck-monitored PG) or TC1303C/TC1304 (dual-monitored PG), the TC1303B variant ties PG exclusively to VOUT2 regulation status and supports independent shutdown of the LDO via SHDN2, enabling flexible power sequencing where the LDO must stabilize before system enablement.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Buck Output Current | 500 mA maximum - supports core voltage rails for ARM Cortex-M microcontrollers and low-power FPGAs |
| LDO Output Current | 300 mA maximum - sufficient for I/O banks, sensors, or RF front-end biasing without external pass devices |
| Quiescent Current | 65 µA typical - enables >1-year battery life in always-on IoT sensor nodes with periodic wake-up |
| PG Monitoring Target | LDO output only (VOUT2) - ensures system reset is triggered only after auxiliary rail stabilization |
| LDO Dropout Voltage | 137 mV typical @ 200 mA - allows operation down to VIN2 = VOUT2 + 0.137 V, critical for Li-ion single-cell designs |
| Switching Frequency | 2.0 MHz fixed - permits use of compact 4.7 µH inductors and reduces EMI filtering footprint |
| Operating Temperature | –40°C to +125°C junction - qualified for automotive cabin and industrial edge controller environments |
Pinout & Package
TC1303B-PA0EUNTR is housed in a 10-pin 3×3 mm DFN package with exposed thermal pad (EP), requiring connection to AGND for thermal and electrical integrity. Pin numbering follows standard DFN orientation (pin 1 top-left, counterclockwise).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| SHDN2 | LDO shutdown control | Active-high logic input (>45% VIN); enables independent LDO disable without affecting buck regulator |
| VIN2 | LDO input supply | Dedicated input for LDO stage; must be tied closely to VIN1 to minimize noise coupling |
| VOUT2 | LDO regulated output | 3.3 V fixed output; requires ≥1 µF ceramic capacitor to AGND for stability |
| PG | Power-good indicator | Push-pull output asserting high when VOUT2 ≥94% of 3.3 V; 300 ms delay prevents premature reset release |
| AGND | Analog ground reference | Separate ground return for feedback and regulation circuitry; must be star-connected to minimize noise |
| VFB1/VOUT1 | Buck feedback or output | Configured as VOUT1 (1.8 V fixed) in this variant; connects directly to buck output node |
| PGND | Power ground | High-current return path for buck switch node (LX); isolated from AGND except at single-point tie |
| LX | Switch node | Connection to internal P/N-channel MOSFETs; requires low-inductance layout to suppress ringing |
| VIN1 | Buck input supply | Main input for buck stage; shared with VIN2 via short PCB trace per datasheet layout guidance |
| SHDN1 | Buck shutdown control | Active-high logic input; independent of SHDN2, allowing staged power-down sequences |
Key Features
| Feature | Design Value |
|---|---|
| Independent LDO shutdown (SHDN2) | Enables selective deactivation of auxiliary rail during sleep modes while maintaining buck output for real-time clocks |
| Push-pull PG output | Eliminates need for external pull-up resistor, reducing BOM count and improving noise immunity vs. open-drain alternatives |
| Internal compensation | Removes requirement for external compensation network, simplifying design and improving production yield |
| 2.0 MHz switching frequency | Reduces required inductor size by ~4× versus 500 kHz solutions, enabling compact 3×3 mm total solution area |
| Thermal shutdown with hysteresis | 165°C trip point with 10°C hysteresis prevents oscillation during transient overload, supporting robust field operation |
Applications
| Portable Medical Sensors | USB-Powered Test Equipment |
|---|---|
Use Scenario: Wearable ECG patch operating from single-cell Li-ion battery with Bluetooth LE transmission. IC Role / Device Role / Timing Role: Dual-rail power source: 1.8 V for MCU and ADC, 3.3 V for BLE radio and analog front-end. Use Value: LDO-monitored PG ensures BLE subsystem only powers up after stable 3.3 V rail is established, preventing radio initialization failures. | Use Scenario: Handheld oscilloscope module powered via USB 2.0 (5 V) with precision analog acquisition chain. IC Role / Device Role / Timing Role: Generates clean 1.8 V digital core supply and low-noise 3.3 V analog supply from USB bus. Use Value: 1.8 µV/√Hz LDO output noise and 62 dB PSRR below 100 Hz preserve signal integrity for 12-bit ADC measurements. |
| Industrial Edge Controller | Low-Power Cellular Modem |
Use Scenario: DIN-rail mounted PLC I/O module with wide ambient temperature range (–40°C to +85°C). IC Role / Device Role / Timing Role: Primary power IC delivering 1.8 V for ARM Cortex-A53 SoC and 3.3 V for CAN transceivers and GPIO expanders. Use Value: –40°C to +125°C junction rating and 41°C/W θJA (DFN) ensure reliable operation without derating in enclosed enclosures. | Use Scenario: NB-IoT tracker using LTE Cat-M1 modem with deep-sleep duty cycling. IC Role / Device Role / Timing Role: Supplies 1.8 V to modem baseband and 3.3 V to SIM interface and GPS receiver. Use Value: 65 µA combined IQ extends battery life in 10-second wake-up intervals; SHDN2 allows modem to gate 3.3 V rail during sleep. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-output PMIC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MCP16311-H/ML | Single-output 600 mA buck only; no integrated LDO or PG monitoring | Requires external LDO and discrete PG circuit for dual-rail systems | Choose when only buck regulation is needed and board space allows discrete support components |
| TPS65023RSBR | Triple-output (2 buck + 1 LDO); PG monitors primary buck; 2.25 MHz switching | Higher integration but lacks LDO-only PG assertion and has larger 4×4 mm QFN package | Prefer when three regulated rails are required and LDO-monitored reset is not mandatory |
Compared with MCP16311-H/ML and TPS65023RSBR, TC1303B-PA0EUNTR uniquely provides LDO-specific power-good assertion with push-pull drive in a compact 3×3 mm DFN, making it optimal for space-constrained dual-rail systems where auxiliary rail stability must trigger system enablement.
Availability
TC1303B-PA0EUNTR is available at Aetrix Electronics and suitable for portable medical sensors, USB-powered test equipment, industrial edge controllers, and low-power cellular modems requiring stable component supply with guaranteed long-term availability.
Supply support for TC1303B-PA0EUNTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a U.S.-based semiconductor company specializing in microcontrollers, analog devices, and power management ICs, with broad industrial and automotive qualification coverage.
The TC1303 family was designed specifically for battery-powered portable electronics needing highly integrated, low-quiescent-current dual-rail power solutions with precise sequencing and monitoring capabilities.
FAQ
What output voltages does the TC1303B-PA0EUNTR provide?
The TC1303B-PA0EUNTR provides two fixed output voltages: 1.8 V from its synchronous buck regulator (VOUT1) and 3.3 V from its low-dropout linear regulator (VOUT2). These values are factory-set and non-adjustable in this variant. The buck output supports up to 500 mA, and the LDO output supports up to 300 mA, both operating from a common 2.7–5.5 V input supply. The TC1303B-PA0EUNTR datasheet confirms these outputs on page 5 (typical application circuit) and page 8 (electrical characteristics table).
How does the power-good (PG) function operate in the TC1303B-PA0EUNTR?
In the TC1303B-PA0EUNTR, the PG pin is a push-pull output that asserts high when the LDO output (VOUT2) reaches and maintains ≥94% of its nominal 3.3 V value, with a built-in 300 ms delay to prevent false triggering during startup transients. This behavior is specific to the TC1303B variant and differs from TC1303A (buck-monitored) and TC1303C/TC1304 (dual-monitored). The TC1303B-PA0EUNTR PG threshold hysteresis is 2% of VOUT2, and its active timeout period is 262 ms typical, as specified in DS21949C-page 9.
Can the TC1303B-PA0EUNTR be used with a single input source for both regulators?
Yes - the TC1303B-PA0EUNTR is designed to operate with VIN1 and VIN2 supplied from the same input source (e.g., a 3.6 V Li-ion battery or 5 V USB rail), as explicitly stated in Note 8 on DS21949C-page 7. The datasheet recommends connecting VIN1 and VIN2 together using short, low-inductance PCB traces to minimize noise coupling and ensure consistent regulation. This configuration is validated in all typical application circuits shown on DS21949C-page 5.
What is the thermal performance of the TC1303B-PA0EUNTR in its DFN package?
The TC1303B-PA0EUNTR in the 10-lead 3×3 mm DFN package has a typical junction-to-ambient thermal resistance (θJA) of 41°C/W on a 4-layer PCB with internal ground plane and two vias under the exposed pad, per DS21949C-page 10. This enables continuous 500 mA buck operation at ambient temperatures up to +85°C without derating when the EP is properly soldered to AGND. Thermal shutdown activates at 165°C with 10°C hysteresis, providing robust protection during overload conditions.
Does the TC1303B-PA0EUNTR require external compensation components?
No - the TC1303B-PA0EUNTR features fully internal compensation for both the buck regulator and the LDO, eliminating the need for external RC networks or type-II/III compensators. This is confirmed in the "Features" section on DS21949C-page 1 and verified in the "Typical Application Circuits" on page 5, where no compensation components appear in either the adjustable or fixed-output schematics. Internal compensation simplifies layout, improves production consistency, and reduces bill-of-materials cost.
TC1303B-PA0EUNTR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Topology:
- Step-Down (Buck) Synchronous (1), Linear (LDO) (1)
- Number of Outputs:
- 2
- Frequency - Switching:
- 2MHz
- Voltage/Current - Output 1:
- 1.8V, 500mA
- Voltage/Current - Output 2:
- 3.3V, 300mA
- Voltage/Current - Output 3:
- -
- w/LED Driver:
- No
- w/Supervisor:
- No
- w/Sequencer:
- Yes
- Voltage - Supply:
- 2.7V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 10-MSOP
TC1303B-PA0EUNTR FAQ
1.How can I place an order for TC1303B-PA0EUNTR through Aetrix?
Please submit a Request for Quotation (RFQ) for TC1303B-PA0EUNTR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TC1303B-PA0EUNTR reliable?
The price and inventory of TC1303B-PA0EUNTR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TC1303B-PA0EUNTR is usually 5 days.
3.What payment methods are accepted for TC1303B-PA0EUNTR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TC1303B-PA0EUNTR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TC1303B-PA0EUNTR?
TC1303B-PA0EUNTR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TC1303B-PA0EUNTR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TC1303B-PA0EUNTR?
For technical support, including TC1303B-PA0EUNTR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TC1303B-PA0EUNTR requirements.
6.How does Aetrix verify that TC1303B-PA0EUNTR is sourced from the original manufacturer or authorized distributors?
All TC1303B-PA0EUNTR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TC1303B-PA0EUNTR meets industry standards.
7.What is the process for return or replacement of TC1303B-PA0EUNTR?
All TC1303B-PA0EUNTR units undergo pre-shipment inspection (PSI). If there is an issue with TC1303B-PA0EUNTR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TC1303B-PA0EUNTR part is unused and in its original packaging.
Return procedure for TC1303B-PA0EUNTR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
TC1303B-PA0EUNTR Tags
-
TPS6521905RHBR
Texas Instruments
-
MIC3385YHL-TR
Microchip Technology
-
A4402ELPTR-T
Allegro MicroSystems
-
LM26480SQ-AA/NOPB
Texas Instruments
-
A4402KLPTR-T
Allegro MicroSystems
-
BD71847AMWV-E2
ROHM Semiconductor
-
ADP5040ACPZ-1-R7
Analog Devices Inc.
-
LT3048IDC#TRPBF
Analog Devices Inc.
-
ADP5037ACPZ-R7
Analog Devices Inc.
-
XRP7714ILB-F
MaxLinear, Inc.
-
LTC3260EDE#TRPBF
Analog Devices Inc.
-
LTC3260EMSE#PBF
Analog Devices Inc.
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
