Microchip Technology TC1303B-PG0EUNTR
- Part No.:
- TC1303B-PG0EUNTR
- Manufacturer:
- Microchip Technology
- Category:
- Voltage Regulators - Linear + Switching
- Package:
- 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
- Datasheet:
-
TC1303B-PG0EUNTR.pdf
- Description:
- IC REG DL BUCK/LNR SYNC 10MSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
TC1303B-PG0EUNTR from Microchip Technology is a dual-output power management IC integrating a 500 mA synchronous buck regulator and a 300 mA low-dropout linear regulator (LDO), with the power-good (PG) output monitoring only the LDO output (VOUT2). It delivers 94% regulation threshold, 137 mV typical dropout at 200 mA for VOUT2, and operates across –40°C to +125°C junction temperature. It targets portable battery-powered systems requiring tightly regulated dual-rail supplies, such as USB-powered medical instruments.
For engineers reviewing the TC1303B-PG0EUNTR datasheet, TC1303B-PG0EUNTR pinout, TC1303B-PG0EUNTR application, or TC1303B-PG0EUNTR equivalent, key selection criteria include its LDO-monitored PG function, independent shutdown control per rail, 2.0 MHz fixed-frequency PWM operation, 65 µA typical quiescent current, and compatibility with 1 µF ceramic output capacitance on VOUT2.
Technical Context
The TC1303B-PG0EUNTR implements a synchronous buck stage with PFM/PWM auto-transition and internal compensation, paired with a standalone LDO stage also internally compensated. Its PG output is push-pull and asserts when VOUT2 reaches ≥94% of nominal, with 300 ms delay used for processor reset sequencing.
It supports independent enable/disable of buck (SHDN1) and LDO (SHDN2) outputs, features undervoltage lockout (2.55 V typical), thermal shutdown (165°C), and short-circuit protection on both outputs. Input voltage range is 2.7 V to 5.5 V, shared across VIN1 and VIN2.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Buck Output Current | 500 mA maximum - supports core logic rails in portable processors without external current boosting |
| LDO Output Current | 300 mA maximum - powers auxiliary I/O, sensors, or interface circuitry with minimal external components |
| PG Monitoring Target | VOUT2 only - enables reliable reset signaling tied specifically to LDO stability, not buck output |
| Quiescent Current | 65 µA typical - extends battery life in always-on or low-power standby modes |
| LDO Dropout Voltage | 137 mV typical @ 200 mA - allows operation with small input–output differentials, e.g., 3.3 V out from 3.44 V input |
| Switching Frequency | 2.0 MHz fixed (typical) - permits use of compact 4.7 µH inductors and reduces EMI fundamental frequency |
| Operating Temp Range | –40°C to +125°C junction - qualified for industrial and extended-temperature embedded applications |
Pinout & Package
TC1303B-PG0EUNTR is housed in a 10-pin 3×3 mm DFN package with exposed pad (EP), thermally connected to AGND. Pin 1 is SHDN2; pin 10 is PG. The exposed pad must be soldered to AGND for thermal and electrical integrity.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 SHDN2 | LDO shutdown control input | Active-high logic (>45% VIN); enables/disables VOUT2 independently of buck stage |
| 2 VIN2 | LDO input supply | Accepts same 2.7–5.5 V input as VIN1; requires low-impedance connection to VIN1 |
| 3 VOUT2 | LDO regulated output | Delivers fixed or adjustable voltage up to 300 mA; requires ≥1 µF ceramic capacitor to AGND |
| 4 PG | Power-good status output | Push-pull output asserting high when VOUT2 ≥94% of nominal; 300 ms delay built-in |
| 5 AGND | Analog ground reference | Primary ground return for feedback, PG, and internal analog circuits; separate from PGND |
| 6 PGND | Power ground return | High-current return path for buck switch node (LX); must be low-inductance, solid plane |
| 7 LX | Buck switch node | Connects to external inductor; carries high di/dt switching current; requires tight layout |
| 8 VIN1 | Buck input supply | Main input for buck stage; shares 2.7–5.5 V source with VIN2; requires local 4.7 µF decoupling |
| 9 SHDN1 | Buck shutdown control input | Active-high logic (>45% VIN); enables/disables VOUT1 independently of LDO stage |
| 10 VFB1/VOUT1 | Buck feedback or output | Configured as output for fixed-VOUT1 variants; as feedback node for adjustable versions (0.8 V ref) |
Key Features
| Feature | Design Value |
|---|---|
| Independent shutdown control | SHDN1 and SHDN2 allow staggered power-up/down of buck and LDO rails for sequencing compliance |
| LDO-monitored power-good | PG asserts only after VOUT2 stabilizes - critical for systems where LDO supplies reset-sensitive peripherals |
| Internally compensated stages | Eliminates need for external compensation networks on either regulator, reducing BOM count and layout complexity |
| Low-noise PFM/PWM transition | Automatic mode switching maintains >90% efficiency at heavy loads and ultra-low IQ (<65 µA) at light loads |
| Robust protection suite | Includes UVLO (2.55 V), thermal shutdown (165°C), overcurrent, and short-circuit protection on both outputs |
Applications
| USB-Powered Medical Instruments | Portable Diagnostic Handhelds |
|---|---|
Use Scenario: Battery-powered glucose meter or pulse oximeter operating from USB 5 V input with strict low-power sleep requirements. IC Role / Device Role / Timing Role: Dual-rail PMIC providing 1.8 V for MCU core (buck) and 3.3 V for sensor interface/LCD driver (LDO), with PG tied to LDO for safe wake-up. Use Value: 65 µA quiescent current extends battery runtime; 1 µF VOUT2 capacitor minimizes board area; LDO-monitored PG prevents false resets during buck transient events. | Use Scenario: Handheld ECG device using single-cell Li-ion (2.7–4.2 V) input, requiring clean 1.2 V core and 2.5 V analog supply. IC Role / Device Role / Timing Role: Buck generates 1.2 V for ARM Cortex-M core; LDO delivers low-noise 2.5 V for ADC reference; PG confirms LDO readiness before data acquisition. Use Value: 137 mV LDO dropout enables full 2.5 V output even at end-of-discharge (2.7 V input); 2.0 MHz switching avoids audible noise in sensitive analog sections. |
| Industrial Portable Data Loggers | Low-Power IoT Edge Sensors |
Use Scenario: Ruggedized field logger with wide-temp operation (–40°C to +85°C ambient), powered by 3.7 V Li-ion. IC Role / Device Role / Timing Role: Provides 3.3 V buck output for microcontroller and 1.8 V LDO output for RF transceiver; PG monitors LDO to gate wireless transmission startup. Use Value: –40°C to +125°C junction rating ensures reliability in uncontrolled environments; independent SHDN pins allow deep-sleep mode where only LDO remains active. | Use Scenario: Wireless environmental sensor node harvesting energy or running on coin cell, requiring ultra-low IQ and fast wake-up. IC Role / Device Role / Timing Role: Buck powers MCU during active sensing; LDO supplies real-time clock and memory; PG signals LDO readiness to initiate measurement sequence. Use Value: 31 µs LDO wake-up time enables rapid response to interrupts; 65 µA total IQ preserves energy budget; push-pull PG eliminates need for external pull-up resistor. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-output PMIC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MCP16311-H/MS | Single-output 1.2 A buck only; no integrated LDO or PG monitoring - requires external LDO and supervisor | Not suitable for LDO-dependent reset sequencing; lacks VOUT2 regulation assurance | Select only if system uses discrete LDO and external reset IC; higher BOM cost and layout area |
| TPS650350RGER | Dual buck (600 mA/300 mA); no integrated LDO; PG monitors primary buck only; 1.2 MHz switching | Cannot replace TC1303B-PG0EUNTR where LDO-supplied peripherals require dedicated PG assertion | Prefer when both rails are switched; avoid when LDO rail must trigger system reset independently |
Compared with MCP16311-H/MS and TPS650350RGER, TC1303B-PG0EUNTR uniquely integrates LDO-monitored PG in a single 3×3 mm DFN, enabling compact, low-component-count designs where LDO stability is the critical power-good condition.
Availability
TC1303B-PG0EUNTR is available at Aetrix Electronics and suitable for USB-powered medical instruments, portable diagnostic handhelds, and industrial data loggers requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for TC1303B-PG0EUNTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a leading provider of microcontrollers, analog devices, and power management ICs, serving industrial, automotive, and consumer markets with high-reliability silicon solutions.
The TC1303 family is designed for space-constrained, battery-operated systems needing efficient dual-rail regulation with intelligent power sequencing and supervision - especially where LDO output stability must govern system reset behavior.
FAQ
What is the power-good (PG) monitoring behavior of TC1303B-PG0EUNTR?
The TC1303B-PG0EUNTR monitors only the LDO output (VOUT2) for power-good assertion. Its PG pin is a push-pull output that goes high when VOUT2 reaches ≥94% of its nominal voltage, with a built-in 300 ms delay. This behavior is fixed for the TC1303B variant and differs from TC1303A (buck-monitored) and TC1303C (dual-monitored). The TC1303B-PG0EUNTR datasheet confirms PG_VOH = 0.9 × VOUT2 under specified load conditions.
Does TC1303B-PG0EUNTR support adjustable output voltage on the buck regulator?
Yes, TC1303B-PG0EUNTR supports adjustable buck output voltage via the VFB1 pin, with an internal 0.8 V reference (±2.5% tolerance). When configured for adjustable mode, external resistive dividers set VOUT1 between 0.8 V and 4.5 V. Fixed-output versions (e.g., 1.2 V, 1.8 V) connect VOUT1 directly to VFB1. The TC1303B-PG0EUNTR pinout and functional block diagram confirm VFB1/VOUT1 as a dual-role terminal.
What is the minimum output capacitance required for the LDO output (VOUT2) of TC1303B-PG0EUNTR?
The TC1303B-PG0EUNTR requires a minimum 1 µF ceramic capacitor on VOUT2 connected to AGND for stable operation and proper load transient response. This value is specified in the Typical Application Circuits and Electrical Characteristics tables of the TC1303B-PG0EUNTR datasheet. Larger values improve PSRR and noise rejection but are not mandatory for basic regulation.
How does TC1303B-PG0EUNTR manage efficiency across load conditions?
The TC1303B-PG0EUNTR uses automatic PWM-to-PFM mode transition in its buck stage: it operates in fixed-frequency 2.0 MHz PWM mode under heavy loads (>~50 mA) for high efficiency (>90%), then seamlessly shifts to PFM at light loads to maintain ultra-low quiescent current (65 µA typical). The LDO stage contributes ~46 µA IQ when active. This dual-mode strategy is intrinsic to the TC1303B-PG0EUNTR architecture and verified in Figure 2-1 of its datasheet.
Can TC1303B-PG0EUNTR operate with separate input sources for VIN1 and VIN2?
No - the TC1303B-PG0EUNTR datasheet explicitly states in Note 8 that "VIN1 and VIN2 are supplied by the same input source." Both inputs must be tied together with short, low-impedance traces. Using separate sources violates absolute maximum ratings and may cause latch-up or improper regulation, as the internal circuitry assumes common input potential. This requirement applies strictly to the TC1303B-PG0EUNTR and all TC1303 variants.
TC1303B-PG0EUNTR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Topology:
- Step-Down (Buck) Synchronous (1), Linear (LDO) (1)
- Number of Outputs:
- 2
- Frequency - Switching:
- 2MHz
- Voltage/Current - Output 1:
- 1.8V, 500mA
- Voltage/Current - Output 2:
- 2.7V, 300mA
- Voltage/Current - Output 3:
- -
- w/LED Driver:
- No
- w/Supervisor:
- No
- w/Sequencer:
- Yes
- Voltage - Supply:
- 2.7V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 10-MSOP
TC1303B-PG0EUNTR FAQ
1.How can I place an order for TC1303B-PG0EUNTR through Aetrix?
Please submit a Request for Quotation (RFQ) for TC1303B-PG0EUNTR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TC1303B-PG0EUNTR reliable?
The price and inventory of TC1303B-PG0EUNTR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TC1303B-PG0EUNTR is usually 5 days.
3.What payment methods are accepted for TC1303B-PG0EUNTR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TC1303B-PG0EUNTR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TC1303B-PG0EUNTR?
TC1303B-PG0EUNTR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TC1303B-PG0EUNTR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TC1303B-PG0EUNTR?
For technical support, including TC1303B-PG0EUNTR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TC1303B-PG0EUNTR requirements.
6.How does Aetrix verify that TC1303B-PG0EUNTR is sourced from the original manufacturer or authorized distributors?
All TC1303B-PG0EUNTR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TC1303B-PG0EUNTR meets industry standards.
7.What is the process for return or replacement of TC1303B-PG0EUNTR?
All TC1303B-PG0EUNTR units undergo pre-shipment inspection (PSI). If there is an issue with TC1303B-PG0EUNTR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TC1303B-PG0EUNTR part is unused and in its original packaging.
Return procedure for TC1303B-PG0EUNTR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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