My Inquiry
My Account
Microchip Technology TC1303B-SA0EMFTR
- Part No.:
- TC1303B-SA0EMFTR
- Manufacturer:
- Microchip Technology
- Category:
- Voltage Regulators - Linear + Switching
- Package:
- 10-VFDFN Exposed Pad
- Datasheet:
-
TC1303B-SA0EMFTR.pdf
- Description:
- IC REG DL BUCK/LINEAR SYNC 10DFN
- Quantity:
- Payment:
- Shipping:
Inventory:4,011
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
TC1303B-SA0EMFTR from Microchip Technology is a dual-output power management IC integrating a 500 mA synchronous buck regulator and a 300 mA low-dropout linear regulator (LDO), with the power-good (PG) output monitoring only the LDO output (VOUT2). It features 2.0 MHz fixed-frequency PWM operation, 65 µA typical quiescent current, 137 mV typical dropout at 200 mA for the LDO, and operates across –40°C to +125°C junction temperature. It is used in portable medical instruments requiring tightly regulated dual-rail supplies with processor reset signaling.
For engineers reviewing the TC1303B-SA0EMFTR datasheet, TC1303B-SA0EMFTR pinout, TC1303B-SA0EMFTR application, or TC1303B-SA0EMFTR equivalent, key selection criteria include LDO-monitored PG behavior, independent shutdown control per rail, internal compensation, 3x3 mm DFN-10 package compatibility, and support for adjustable or fixed VOUT1 (0.8–4.5 V) and standard VOUT2 (1.5/1.8/2.5/3.3 V) outputs.
Technical Context
The TC1303B-SA0EMFTR implements a synchronous buck regulator with automatic PWM-to-PFM mode transition under light load to maintain ultra-low quiescent current, while its LDO uses a single 1 µF ceramic output capacitor and delivers stable 300 mA with minimal dropout. Its PG output is push-pull (not open-drain) and asserts only when VOUT2 reaches ≥94% of regulation, with 300 ms delay-designed specifically for processor reset timing in battery-powered systems.
Unlike TC1303A (PG monitors buck only) or TC1303C/TC1304 (PG monitors both rails), the TC1303B variant exclusively ties PG to VOUT2 regulation status. Shutdown logic is independent: SHDN1 controls the buck regulator, SHDN2 controls the LDO, enabling flexible power sequencing without external circuitry.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Configuration | Dual-output: 500 mA buck + 300 mA LDO, with PG tied solely to LDO (VOUT2) |
| Switching Frequency | 2.0 MHz fixed PWM (heavy load); auto transitions to PFM at light load to minimize IQ |
| Quiescent Current | 65 µA typical total device IQ enables >100-hour standby in coin-cell–powered devices |
| LDO Dropout Voltage | 137 mV typical @ 200 mA - supports 1.8 V output from 2.0 V input |
| Power-Good Output | Push-pull PG with 300 ms delay; active-high when VOUT2 ≥94% of nominal |
| Operating Temperature | –40°C to +125°C junction range - qualified for industrial and medical environments |
| Package | 3×3 mm, 10-pin DFN (exposed pad tied to AGND) - thermal resistance θJA = 41°C/W |
Pinout & Package
TC1303B-SA0EMFTR is housed in a 3×3 mm, 10-pin DFN package with exposed thermal pad (EP) connected to AGND. Pin numbering follows standard DFN orientation (pin 1 top-left, counterclockwise).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (SHDN2) | LDO shutdown control input | Active-high logic input (>45% VIN enables LDO; <15% VIN disables it) |
| 2 (VIN2) | LDO input supply | Accepts 2.7–5.5 V; must be short-traced to VIN1 to minimize noise coupling |
| 3 (VOUT2) | LDO regulated output | Delivers up to 300 mA; requires ≥1 µF ceramic capacitor to AGND |
| 4 (PG) | Power-good indicator | Push-pull output asserting high when VOUT2 is within 94–96% of target; 300 ms delay built-in |
| 5 (AGND) | Analog ground reference | Must connect to clean analog ground plane; separate from PGND for noise isolation |
| 6 (PGND) | Power ground return | High-current return path for buck switch node; tie to AGND only at single point near EP |
| 7 (LX) | Buck switch node | Connects to external 4.7 µH inductor; carries high di/dt switching current |
| 8 (VIN1) | Buck input supply | Accepts 2.7–5.5 V; shared with VIN2 in most designs |
| 9 (SHDN1) | Buck shutdown control input | Independent active-high enable for buck regulator; allows staggered startup |
| 10 (VFB1/VOUT1) | Buck feedback or output | Configurable: for adjustable VOUT1, connect voltage divider center here; for fixed output, connect directly to VOUT1 |
Key Features
| Feature | Design Value |
|---|---|
| Independent shutdown control | SHDN1 and SHDN2 allow precise sequencing of buck and LDO rails - critical for FPGA or multi-core SoC power-up order |
| Internally compensated regulators | Eliminates need for external compensation components - reduces BOM count and layout complexity |
| Low-noise buck architecture | 2.0 MHz fixed frequency + integrated MOSFETs minimize EMI and enable use of small 4.7 µH inductors |
| Ultra-low dropout LDO | 137 mV typical dropout at 200 mA enables efficient 1.8 V generation from 2.0 V battery sources |
| Robust protection suite | Includes UVLO (2.55 V threshold), overtemperature shutdown (165°C), and short-circuit protection on both outputs |
Applications
| Portable Medical Sensors | USB-Powered Diagnostic Tools |
|---|---|
Use Scenario: Handheld blood glucose meter with Bluetooth LE connectivity and LCD display. IC Role / Device Role / Timing Role: Provides 1.8 V core supply (buck) for MCU and 3.3 V I/O rail (LDO) for BLE transceiver and display driver; PG asserts reset to MCU after LDO stabilizes. Use Value: 65 µA quiescent current extends battery life beyond 12 months on two AAA cells; 300 mA LDO supports peak BLE transmit current without droop. | Use Scenario: USB bus-powered ECG front-end module with analog signal chain and microcontroller. IC Role / Device Role / Timing Role: Generates 2.5 V analog supply (LDO) and 1.2 V digital core (buck); PG monitors LDO to ensure analog section is fully powered before ADC sampling begins. Use Value: LDO-monitored PG guarantees analog rail stability prior to data acquisition - eliminates measurement offset errors during power ramp. |
| Industrial Handheld Terminals | Wearable Health Monitors |
Use Scenario: Ruggedized barcode scanner with cold-temperature operation requirement. IC Role / Device Role / Timing Role: Supplies 3.3 V LDO rail for imager interface and 1.5 V buck rail for ARM Cortex-M4; PG triggers system boot only after LDO reaches regulation in –30°C ambient. Use Value: –40°C to +125°C operating range and push-pull PG ensure reliable startup in freezer environments where open-drain PG would fail to drive logic thresholds. | Use Scenario: Continuous heart-rate monitor using photoplethysmography (PPG) with rechargeable Li-ion battery. IC Role / Device Role / Timing Role: Delivers 1.8 V (buck) to sensor ASIC and 2.5 V (LDO) to analog front-end; independent SHDN2 allows dynamic LDO disable during sleep to cut leakage. Use Value: Independent LDO shutdown reduces system sleep current to <1 µA - extending wearable runtime to 7+ days per charge. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-output PMIC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TC1303A-SA0EMFTR | PG monitors buck output (VOUT1), not LDO; same pinout and electrical specs otherwise | Suitable when system reset depends on core voltage stabilization, not I/O rail | Select TC1303A if primary reset trigger is MCU core supply; verify PG timing aligns with buck startup profile |
| TPS65023RSBR | Triple-output (2 buck + 1 LDO), 2.25 MHz switching, higher IQ (120 µA), QFN-24 package | Supports more complex SoC power trees but requires larger PCB area and additional passives | Choose TPS65023RSBR only when third rail (e.g., memory I/O) is required; not drop-in compatible due to pin count and footprint |
Compared with TC1303A-SA0EMFTR and TPS65023RSBR, the TC1303B-SA0EMFTR uniquely provides LDO-monitored PG in a compact 10-pin DFN - making it optimal for space-constrained, single-LDO-dependent reset architectures where minimal IQ and proven medical-grade reliability are mandatory.
Availability
TC1303B-SA0EMFTR is available at Aetrix Electronics and suitable for portable medical sensors, USB-powered diagnostic tools, and industrial handheld terminals requiring stable component supply, long-term lifecycle support, and guaranteed traceability.
Supply support for TC1303B-SA0EMFTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a leading provider of microcontrollers, analog components, and power management ICs, with a focus on reliability, longevity, and embedded system integration.
The TC1303 family was designed specifically for battery-powered portable electronics needing dual-rail power with intelligent sequencing and ultra-low quiescent current - targeting medical, industrial, and consumer handheld applications.
FAQ
What is the power-good (PG) behavior of TC1303B-SA0EMFTR?
The TC1303B-SA0EMFTR features a push-pull PG output that monitors only the LDO output (VOUT2). It asserts high when VOUT2 reaches ≥94% of its nominal value, with a fixed 300 ms delay - designed explicitly for processor reset timing. This differs from TC1303A (PG monitors buck) and TC1303C/TC1304 (PG monitors both rails). The TC1303B-SA0EMFTR's PG behavior ensures system reset occurs only after the I/O or analog rail is fully stabilized.
Can TC1303B-SA0EMFTR support adjustable VOUT1?
Yes, TC1303B-SA0EMFTR supports adjustable VOUT1 from 0.8 V to 4.5 V via external resistor divider connected to the VFB1/VOUT1 pin. The internal feedback reference is 0.8 V ±2.5%, and the device is internally compensated - no external compensation components are needed. Fixed-output versions (e.g., 1.2 V, 1.5 V, 1.8 V) are also available, but TC1303B-SA0EMFTR specifically uses the adjustable configuration.
What is the thermal performance of TC1303B-SA0EMFTR in its DFN package?
TC1303B-SA0EMFTR in the 3×3 mm DFN-10 package has a typical junction-to-ambient thermal resistance (θJA) of 41°C/W on a 4-layer board with internal ground plane and two vias in the exposed pad. This enables full 500 mA buck + 300 mA LDO operation up to +85°C ambient without derating, provided the EP is soldered to AGND. Thermal shutdown activates at +165°C with 10°C hysteresis.
How does TC1303B-SA0EMFTR manage efficiency across load conditions?
TC1303B-SA0EMFTR uses automatic PWM-to-PFM mode transition in its buck regulator: at heavy loads (>100 mA), it operates in fixed 2.0 MHz PWM for low noise and high efficiency (>90% typical); at light loads, it switches to PFM to reduce quiescent current to 38 µA (buck-only) and maintain >80% efficiency down to 1 mA. This preserves battery life in intermittent-use applications like portable diagnostics.
Is TC1303B-SA0EMFTR pin-compatible with other TC1303 variants?
Yes, TC1303B-SA0EMFTR is pin-compatible with TC1303A, TC1303C, and TC1304 in both DFN-10 and MSOP-10 packages - same pinout, same footprint, same electrical ratings. The only functional difference is PG monitoring scope (LDO-only for TC1303B), which requires no PCB change but may necessitate firmware or timing validation in systems relying on PG assertion timing.
TC1303B-SA0EMFTR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 10-VFDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Topology:
- Step-Down (Buck) Synchronous (1), Linear (LDO) (1)
- Number of Outputs:
- 2
- Frequency - Switching:
- 2MHz
- Voltage/Current - Output 1:
- 1.5V, 500mA
- Voltage/Current - Output 2:
- 3.3V, 300mA
- Voltage/Current - Output 3:
- -
- w/LED Driver:
- No
- w/Supervisor:
- No
- w/Sequencer:
- Yes
- Voltage - Supply:
- 2.7V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 10-DFN (3x3)
TC1303B-SA0EMFTR FAQ
1.How can I place an order for TC1303B-SA0EMFTR through Aetrix?
Please submit a Request for Quotation (RFQ) for TC1303B-SA0EMFTR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TC1303B-SA0EMFTR reliable?
The price and inventory of TC1303B-SA0EMFTR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TC1303B-SA0EMFTR is usually 5 days.
3.What payment methods are accepted for TC1303B-SA0EMFTR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TC1303B-SA0EMFTR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TC1303B-SA0EMFTR?
TC1303B-SA0EMFTR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TC1303B-SA0EMFTR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TC1303B-SA0EMFTR?
For technical support, including TC1303B-SA0EMFTR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TC1303B-SA0EMFTR requirements.
6.How does Aetrix verify that TC1303B-SA0EMFTR is sourced from the original manufacturer or authorized distributors?
All TC1303B-SA0EMFTR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TC1303B-SA0EMFTR meets industry standards.
7.What is the process for return or replacement of TC1303B-SA0EMFTR?
All TC1303B-SA0EMFTR units undergo pre-shipment inspection (PSI). If there is an issue with TC1303B-SA0EMFTR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TC1303B-SA0EMFTR part is unused and in its original packaging.
Return procedure for TC1303B-SA0EMFTR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
TC1303B-SA0EMFTR Tags
-
TPS6521905RHBR
Texas Instruments
-
MIC3385YHL-TR
Microchip Technology
-
A4402ELPTR-T
Allegro MicroSystems
-
LM26480SQ-AA/NOPB
Texas Instruments
-
A4402KLPTR-T
Allegro MicroSystems
-
BD71847AMWV-E2
ROHM Semiconductor
-
ADP5040ACPZ-1-R7
Analog Devices Inc.
-
LT3048IDC#TRPBF
Analog Devices Inc.
-
ADP5037ACPZ-R7
Analog Devices Inc.
-
XRP7714ILB-F
MaxLinear, Inc.
-
LTC3260EDE#TRPBF
Analog Devices Inc.
-
LTC3260EMSE#PBF
Analog Devices Inc.
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
