Microchip Technology TC1303B-ZI0EMFTR
- Part No.:
- TC1303B-ZI0EMFTR
- Manufacturer:
- Microchip Technology
- Category:
- Voltage Regulators - Linear + Switching
- Package:
- 10-VFDFN Exposed Pad
- Datasheet:
-
TC1303B-ZI0EMFTR.pdf
- Description:
- IC REG DL BUCK/LINEAR SYNC 10DFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
TC1303B-ZI0EMFTR from Microchip Technology is a dual-output power management IC integrating a 500 mA synchronous buck regulator and a 300 mA low-dropout linear regulator (LDO), with power-good monitoring specifically of the LDO output. It delivers 94% regulation threshold detection, 137 mV typical dropout at 200 mA for VOUT2, and operates across –40°C to +125°C junction temperature. It targets portable battery-powered systems requiring tightly regulated dual rails, such as USB-powered medical instruments.
For engineers reviewing the TC1303B-ZI0EMFTR datasheet, TC1303B-ZI0EMFTR pinout, TC1303B-ZI0EMFTR application, or TC1303B-ZI0EMFTR equivalent, key selection criteria include its LDO-monitored PG function, independent SHDN2 control, 2.0 MHz fixed-frequency PWM operation with automatic PFM transition, 65 µA typical quiescent current, and DFN/MSOP package compatibility with 3x3 mm footprint constraints.
Technical Context
The TC1303B-ZI0EMFTR implements a synchronous buck stage with integrated P-channel and N-channel MOSFETs (RDS(on) = 450 mΩ each), operating at 2.0 MHz nominal switching frequency under heavy load and transitioning automatically to PFM mode at light loads to maintain ultra-low IQ. Its LDO stage uses internal compensation and achieves 137 mV dropout at 200 mA with ±0.3% output voltage tolerance.
Power-good logic monitors only the LDO output (VOUT2) with 94% high-threshold and 92% low-threshold hysteresis, generating a push-pull PG signal with 262 ms active timeout and 165 µs delay. Shutdown is independently controlled via SHDN1 (buck) and SHDN2 (LDO), each with defined VIH/VIL thresholds referenced to VIN.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Buck Output Current | 500 mA max - supports processor core or SoC I/O rail with minimal external components |
| LDO Output Current | 300 mA max - powers auxiliary circuits like sensors or interface ICs with low noise |
| Quiescent Current | 65 µA typical - enables multi-week battery life in always-on portable devices |
| LDO Dropout Voltage | 137 mV @ 200 mA - allows operation down to 2.7 V input while regulating 2.5 V or 3.3 V outputs |
| Switching Frequency | 2.0 MHz fixed (heavy load) - permits use of small 4.7 µH inductors and compact 4.7 µF ceramic output capacitors |
| PG Monitoring Target | VOUT2 only - ensures system reset is asserted only when LDO rail is valid, critical for mixed-voltage sequencing |
| Operating Temp Range | –40°C to +125°C - qualified for industrial and automotive-adjacent portable equipment environments |
Pinout & Package
TC1303B-ZI0EMFTR is available in a 10-pin 3×3 mm DFN package with exposed thermal pad (EP), pin-compatible with the MSOP variant. The DFN variant requires EP connection to AGND for thermal and electrical integrity.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| SHDN2 | LDO shutdown control input | Active-high logic input (>45% VIN); enables independent LDO disable without affecting buck stage |
| VIN2 | LDO input supply | Accepts same 2.7–5.5 V input as VIN1; must be routed with minimal trace length to VIN1 |
| VOUT2 | LDO regulated output | Delivers fixed 1.5 V, 1.8 V, 2.5 V, or 3.3 V; requires ≥1 µF ceramic capacitor to AGND |
| PG | Power-good status output | Push-pull output indicating VOUT2 is within 94–96% of target; drives processor RESET directly |
| AGND | Analog ground reference | Must be tied to clean analog ground plane; separate from PGND to minimize noise coupling |
| PGND | Power ground return | High-current return path for buck switch node; connects to power ground plane near LX and VIN1 |
| LX | Buck switch node | Connects to external inductor; contains fast-switching edges requiring tight layout and ground stitching |
| VIN1 | Buck input supply | Primary input for buck stage; shares 2.7–5.5 V source with VIN2; requires local 4.7 µF decoupling |
| SHDN1 | Buck shutdown control input | Active-high logic input (>45% VIN); allows independent buck disable during low-power states |
| VFB1/VOUT1 | Buck feedback or output | Configurable: connect to divider midpoint for adjustable output (0.8–4.5 V), or directly to VOUT1 for fixed options |
Key Features
| Feature | Design Value |
|---|---|
| Independent buck/LDO shutdown | Enables selective power gating: e.g., keep LDO active for RTC while shutting down buck for CPU sleep |
| PG monitors LDO only | Prevents false resets caused by buck transient; guarantees auxiliary rail stability before system wake-up |
| Internally compensated LDO | Eliminates need for external compensation network; reduces BOM count and layout area |
| Automatic PWM-to-PFM transition | Maintains >85% efficiency down to 1 mA load without firmware intervention or mode control pins |
| Thermal/UVLO/short-circuit protection | Self-protects under fault conditions; eliminates need for external supervision circuitry in space-constrained designs |
Applications
| USB-Powered Medical Instruments | Portable Computers |
|---|---|
Use Scenario: Handheld glucose meters or ECG monitors powered via USB 5 V input. IC Role / Device Role / Timing Role: Generates 3.3 V for MCU and 1.8 V for analog front-end ADC from single USB source. Use Value: LDO-monitored PG ensures ADC bias rail is stable before sampling begins, preventing measurement corruption. | Use Scenario: Subnotebook or tablet companion device with dual-core application processor. IC Role / Device Role / Timing Role: Supplies 1.2 V core and 3.3 V I/O rails; SHDN1/SHDN2 enable dynamic power partitioning. Use Value: Independent shutdown lets OS power down core rail while maintaining I/O rail for wake-on-LAN or USB suspend/resume. |
| Cellular Phones | Handheld Organizers & PDAs |
Use Scenario: Feature phone baseband subsystem requiring low-noise 2.5 V and efficient 1.5 V supplies. IC Role / Device Role / Timing Role: Buck powers RF transceiver; LDO powers sensitive PLL/VCO circuitry. Use Value: 1.8 µV/√Hz LDO output noise prevents phase jitter degradation in RF synthesizers. | Use Scenario: Legacy PDA with ARM9 processor, touchscreen controller, and flash memory. IC Role / Device Role / Timing Role: Delivers 1.8 V for SDRAM interface and 3.3 V for SD card slot from single Li-ion cell (3.0–4.2 V). Use Value: 137 mV LDO dropout enables full 3.3 V regulation even at end-of-discharge battery voltage (3.0 V). |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-output PMIC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TC1303C-ZI0EMFTR | Monitors both buck and LDO outputs for PG assertion; open-drain PG output | Required where system reset must wait for both rails to stabilize (e.g., FPGA configuration) | Select when coordinated power-rail validation is mandatory; not drop-in due to PG logic change |
| TPS65023BRSBR | Triple-output (2 buck + 1 LDO); higher 1.2 A buck current; I²C programmable; 4×4 QFN | Suitable for more complex SoC power trees needing dynamic voltage scaling | Choose when additional output or digital control is needed; larger footprint and higher cost |
Compared with TC1303C-ZI0EMFTR and TPS65023BRSBR, the TC1303B-ZI0EMFTR provides optimal simplicity and size for LDO-critical applications-its dedicated LDO-monitored PG and 3×3 mm DFN make it ideal where auxiliary rail integrity dictates system readiness, without over-engineering for multi-rail coordination or programmability.
Availability
TC1303B-ZI0EMFTR is available at Aetrix Electronics and suitable for USB-powered medical instruments, portable computers, and handheld organizers requiring stable component supply with guaranteed long-term manufacturability.
Supply support for TC1303B-ZI0EMFTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a U.S.-based semiconductor company specializing in microcontrollers, analog devices, and power management ICs for embedded control applications.
The TC1303 family was designed to deliver highly integrated, low-quiescent-current dual-rail power solutions for space- and battery-life-constrained portable electronics, emphasizing simplicity, reliability, and minimal external component count.
FAQ
What is the power-good (PG) monitoring behavior of the TC1303B-ZI0EMFTR?
The TC1303B-ZI0EMFTR monitors only the LDO output (VOUT2) for power-good assertion. Its PG pin is a push-pull output that goes high when VOUT2 reaches ≥94% of its nominal value and remains high until VOUT2 falls below 92%. This behavior is fixed per the TC1303B variant and differs from TC1303A (buck-only monitoring) and TC1303C (dual-rail monitoring). The TC1303B-ZI0EMFTR's PG timing includes a 262 ms active timeout and 165 µs response delay.
Can the TC1303B-ZI0EMFTR generate adjustable buck output voltages?
Yes, the TC1303B-ZI0EMFTR supports adjustable buck output from 0.8 V to 4.5 V using an external resistor divider connected to the VFB1/VOUT1 pin. The internal feedback reference is 0.8 V ±2.5%, and the device maintains ±0.3% output voltage tolerance across load and temperature. Fixed-output versions (e.g., 1.2 V, 1.5 V, 1.8 V) are also available, but the TC1303B-ZI0EMFTR itself is configured for adjustable operation per its part number suffix and datasheet specification.
What is the thermal performance of the TC1303B-ZI0EMFTR in its DFN package?
The TC1303B-ZI0EMFTR in the 10-lead 3×3 mm DFN package has a typical junction-to-ambient thermal resistance (θJA) of 41°C/W on a 4-layer PCB with internal ground plane and two vias in the exposed pad. Thermal shutdown activates at 165°C with 10°C hysteresis. To maintain safe operation at full 500 mA buck and 300 mA LDO load, the board must implement proper copper pour and thermal via placement beneath the EP pad, tied directly to AGND.
How does the TC1303B-ZI0EMFTR manage efficiency at light loads?
The TC1303B-ZI0EMFTR automatically transitions from fixed-frequency 2.0 MHz PWM mode to pulse-frequency modulation (PFM) mode when buck load drops below ~10 mA. This preserves >85% efficiency down to 1 mA load while reducing quiescent current to 65 µA typical. No external control or mode-select pins are required-the transition is seamless and internally managed, making it ideal for battery-powered devices with intermittent processing bursts.
What are the recommended input and output capacitors for the TC1303B-ZI0EMFTR?
For the buck stage, use a 4.7 µH shielded inductor and 4.7 µF X5R/X7R ceramic input/output capacitors rated ≥6.3 V. For the LDO stage, a minimum 1.0 µF X5R/X7R ceramic capacitor is required on VOUT2 to AGND; 2.2 µF improves transient response. All capacitors must be placed within 2 mm of their respective pins, with short, wide traces to PGND/AGND. The DFN's exposed pad must be soldered and connected to AGND with ≥4 thermal vias.
TC1303B-ZI0EMFTR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 10-VFDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Topology:
- Step-Down (Buck) Synchronous (1), Linear (LDO) (1)
- Number of Outputs:
- 2
- Frequency - Switching:
- 2MHz
- Voltage/Current - Output 1:
- Adj, 500mA
- Voltage/Current - Output 2:
- 2.5V, 300mA
- Voltage/Current - Output 3:
- -
- w/LED Driver:
- No
- w/Supervisor:
- No
- w/Sequencer:
- Yes
- Voltage - Supply:
- 2.7V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 10-DFN (3x3)
TC1303B-ZI0EMFTR FAQ
1.How can I place an order for TC1303B-ZI0EMFTR through Aetrix?
Please submit a Request for Quotation (RFQ) for TC1303B-ZI0EMFTR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TC1303B-ZI0EMFTR reliable?
The price and inventory of TC1303B-ZI0EMFTR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TC1303B-ZI0EMFTR is usually 5 days.
3.What payment methods are accepted for TC1303B-ZI0EMFTR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TC1303B-ZI0EMFTR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TC1303B-ZI0EMFTR?
TC1303B-ZI0EMFTR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TC1303B-ZI0EMFTR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TC1303B-ZI0EMFTR?
For technical support, including TC1303B-ZI0EMFTR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TC1303B-ZI0EMFTR requirements.
6.How does Aetrix verify that TC1303B-ZI0EMFTR is sourced from the original manufacturer or authorized distributors?
All TC1303B-ZI0EMFTR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TC1303B-ZI0EMFTR meets industry standards.
7.What is the process for return or replacement of TC1303B-ZI0EMFTR?
All TC1303B-ZI0EMFTR units undergo pre-shipment inspection (PSI). If there is an issue with TC1303B-ZI0EMFTR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TC1303B-ZI0EMFTR part is unused and in its original packaging.
Return procedure for TC1303B-ZI0EMFTR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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