Microchip Technology TC1303B-ZP0EUNTR
- Part No.:
- TC1303B-ZP0EUNTR
- Manufacturer:
- Microchip Technology
- Category:
- Voltage Regulators - Linear + Switching
- Package:
- 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
- Datasheet:
-
TC1303B-ZP0EUNTR.pdf
- Description:
- IC REG DL BUCK/LNR SYNC 10MSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
TC1303B-ZP0EUNTR from Microchip Technology is a dual-output power management IC integrating a 500 mA synchronous buck regulator and a 300 mA low-dropout linear regulator (LDO), with power-good monitoring specifically tied to the LDO output. It delivers 1.8 V at 500 mA (VOUT1) and 3.3 V at 300 mA (VOUT2), operates from 2.7–5.5 V input, and features 65 µA typical quiescent current and 2.0 MHz fixed-frequency PWM switching - ideal for portable medical instruments and USB-powered devices requiring tightly regulated dual-rail supplies.
For engineers reviewing the TC1303B-ZP0EUNTR datasheet, TC1303B-ZP0EUNTR pinout, TC1303B-ZP0EUNTR application, or TC1303B-ZP0EUNTR equivalent, key selection criteria include its LDO-monitored PG output, independent SHDN1/SHDN2 control, 137 mV typical dropout at 200 mA, internal compensation, and operation across –40°C to +125°C junction temperature.
Technical Context
The TC1303B-ZP0EUNTR implements a synchronous buck topology with PFM mode transition under light load to maintain ultra-low IQ, while its LDO uses a single 1 µF ceramic output capacitor and achieves ±0.3% output voltage tolerance. The power-good signal is a push-pull output referenced exclusively to VOUT2 regulation with 94% threshold and 300 ms active timeout.
Its shutdown architecture separates control of the buck (SHDN1) and LDO (SHDN2), enabling flexible sequencing; UVLO activates at 2.55 V (typical) with 200 mV hysteresis, and thermal protection triggers at 165°C with 10°C hysteresis. Both regulators include overcurrent and short-circuit protection.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.7 V to 5.5 V - supports single-cell Li-ion (2.7–4.2 V) and USB 5 V rails without external pre-regulation |
| Buck Output (VOUT1) | Adjustable 0.8–4.5 V or fixed 1.8 V @ 500 mA - configured as 1.8 V in this variant; ±0.3% tolerance ensures core voltage stability |
| LDO Output (VOUT2) | Fixed 3.3 V @ 300 mA - 137 mV typical dropout at 200 mA enables high-efficiency biasing from low-headroom inputs |
| Quiescent Current | 65 µA typical total - enables >1-year battery life in always-on portable systems with both outputs active |
| Power-Good Output | Push-pull, monitors VOUT2 only - asserts high when VOUT2 reaches 94% of 3.3 V; 300 ms timeout supports processor reset timing |
| Switching Frequency | 2.0 MHz (±0.4 MHz) - allows use of compact 4.7 µH inductors and reduces EMI above AM band |
| Operating Temperature | –40°C to +125°C junction - qualified for industrial and automotive under-hood auxiliary supply applications |
Pinout & Package
TC1303B-ZP0EUNTR is housed in a 10-lead 3×3 mm DFN package with exposed pad (EP) connected to AGND. Pin assignments are validated per Microchip DS21949C-page 3 and page 5 schematic diagrams.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (SHDN2) | LDO shutdown control | Active-high logic input (>45% VIN); enables/disables 3.3 V LDO independently of buck stage |
| 2 (VIN2) | LDO input supply | Accepts same input as VIN1; must be routed with minimal trace length to reduce noise coupling into LDO |
| 3 (VOUT2) | LDO regulated output | 3.3 V rail; requires ≥1 µF ceramic capacitor to AGND for stability and transient response |
| 4 (PG) | Power-good indicator | Push-pull output asserting high when VOUT2 is within 94–96% of 3.3 V; drives processor RESET directly |
| 5 (AGND) | Analog ground reference | Must be connected to clean analog ground plane; separate from PGND to minimize switching noise injection |
| 6 (PGND) | Power ground return | High-current return path for buck switch node; ties to AGND only at single point near EP |
| 7 (LX) | Buck switch node | Connects to external 4.7 µH inductor; requires low-inductance layout to minimize ringing and EMI |
| 8 (VIN1) | Buck input supply | Main input for synchronous buck; shares source with VIN2 but routed separately for optimal decoupling |
| 9 (SHDN1) | Buck shutdown control | Active-high logic input; independent enable for 1.8 V buck output enables dynamic power gating |
| 10 (VFB1/VOUT1) | Buck feedback/sense | Configured as VOUT1 (not adjustable) in ZP0EUNTR; connects directly to 1.8 V output for regulation |
Key Features
| Feature | Design Value |
|---|---|
| Independent dual shutdown control | SHDN1 and SHDN2 allow staggered enable/disable of 1.8 V and 3.3 V rails - essential for I/O and core power sequencing |
| Internal compensation | Eliminates need for external compensation network on either regulator - reduces BOM count and layout area |
| Low-noise 2.0 MHz PWM | Enables use of small, low-ESR ceramic capacitors and avoids audible noise; PFM mode maintains <100 µA IQ at light loads |
| LDO-monitored power-good | PG asserts only after VOUT2 stabilizes - ensures reliable reset assertion for peripherals powered by 3.3 V rail |
| Thermal and short-circuit protection | Auto-recovery shutdown at 165°C junction and 240 mA average short-circuit current limit - prevents damage during fault conditions |
Applications
| Portable Medical Sensors | USB-Powered Test Equipment |
|---|---|
Use Scenario: Battery-operated glucose meter with LCD display and Bluetooth LE radio. IC Role / Device Role / Timing Role: Provides 1.8 V for MCU core and 3.3 V for display driver/radio transceiver; PG signal resets system if 3.3 V rail fails. Use Value: 65 µA total IQ extends AA battery life beyond 18 months; 137 mV LDO dropout enables full 3.3 V output down to 3.43 V input. | Use Scenario: Handheld oscilloscope powered via USB 5 V port with FPGA-based signal processing. IC Role / Device Role / Timing Role: Generates 1.8 V for FPGA core and 3.3 V for ADC interface and USB PHY; independent SHDN pins enable FPGA-controlled power states. Use Value: 2.0 MHz switching minimizes inductor size (<2 mm × 2 mm), enabling compact 3.5" form factor; ±0.3% VOUT2 tolerance ensures ADC reference stability. |
| Industrial Handheld Terminals | Wearable Health Monitors |
Use Scenario: Ruggedized barcode scanner operating in cold storage (-20°C) and warehouse heat (+50°C). IC Role / Device Role / Timing Role: Supplies 1.8 V to ARM Cortex-M4 and 3.3 V to imager sensor and Wi-Fi module; PG output triggers firmware watchdog reset on rail collapse. Use Value: –40°C to +125°C junction rating guarantees operation across ambient extremes; 113°C/W θJA (MSOP) or 41°C/W (DFN) enables passive cooling. | Use Scenario: ECG patch with continuous 24/7 sensing, BLE streaming, and coin-cell battery. IC Role / Device Role / Timing Role: Delivers 1.8 V to ultra-low-power MCU and 3.3 V to analog front-end; PFM mode reduces IQ to <30 µA during sleep cycles. Use Value: 1 µF LDO output cap requirement minimizes footprint; 300 mA LDO output supports simultaneous sensor biasing and RF transmission bursts. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-output PMIC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MCP16311-H/MS | Single 600 mA buck only; no integrated LDO or PG - requires external LDO and supervisor IC | Suitable only when LDO rail is non-critical or can be added externally; lacks LDO-monitored PG | Select if cost-sensitive design can tolerate higher component count and board area; not drop-in |
| TPS65023RGZR | Triple-output (2 buck + 1 LDO); 2.25 MHz switching; PG monitors buck1 only; 16-pin QFN | Supports more complex SoC power trees; PG does not monitor LDO output - incompatible for LDO-failure detection | Choose when needing third rail or higher integration; verify PG logic matches system reset requirements |
Compared with MCP16311-H/MS and TPS65023RGZR, TC1303B-ZP0EUNTR uniquely provides LDO-specific power-good assertion, independent dual shutdown, and minimal 10-pin DFN footprint - making it optimal for space-constrained, dual-rail portable systems where LDO rail integrity is critical to system boot and operation.
Availability
TC1303B-ZP0EUNTR is available at Aetrix Electronics and suitable for portable medical instruments, USB-powered test equipment, and industrial handheld terminals requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.
Supply support for TC1303B-ZP0EUNTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a leading provider of microcontrollers, analog components, and power management ICs, serving industrial, automotive, and consumer markets with high-reliability silicon and comprehensive design support.
TC1303B-ZP0EUNTR belongs to Microchip's TC1303 series of dual-output PMICs designed specifically for battery-powered portable electronics requiring efficient, sequenced, and monitored dual-voltage regulation with minimal external components.
FAQ
What is the power-good (PG) behavior of TC1303B-ZP0EUNTR?
The TC1303B-ZP0EUNTR features a push-pull PG output that monitors only the LDO output (VOUT2 = 3.3 V). It asserts high when VOUT2 reaches 94% of nominal (3.102 V), remains active for a 300 ms timeout period, and pulls low if VOUT2 drops below 92% (3.036 V). This behavior is confirmed in DS21949C-page 9 and distinguishes TC1303B-ZP0EUNTR from TC1303A (buck-monitored) and TC1303C (dual-monitored) variants.
Can TC1303B-ZP0EUNTR operate with separate input sources for VIN1 and VIN2?
No - TC1303B-ZP0EUNTR requires VIN1 and VIN2 to be supplied from the same input source, as explicitly stated in DS21949C-page 7 Note 8. Routing them from independent supplies violates the device's internal biasing and may cause regulation instability or undefined PG behavior. Board layout must tie VIN1 and VIN2 together with short, low-impedance traces.
What is the minimum output capacitor required for VOUT2 on TC1303B-ZP0EUNTR?
The TC1303B-ZP0EUNTR requires a minimum 1 µF ceramic capacitor between VOUT2 and AGND for stable LDO operation, as specified in DS21949C-page 5 typical application circuit and page 3 functional block diagram notes. Using smaller or non-ceramic types risks oscillation, poor load transient response, and failure to meet ±0.3% output tolerance under load steps.
Does TC1303B-ZP0EUNTR support adjustable VOUT1 output voltage?
No - TC1303B-ZP0EUNTR is a fixed-output variant with VOUT1 = 1.8 V. Its part number suffix "ZP0" denotes fixed 1.8 V buck output and fixed 3.3 V LDO output, per Microchip's TC1303 ordering guide. The VFB1 pin is internally connected to VOUT1; external resistor dividers are not supported in this configuration.
How does thermal protection work on TC1303B-ZP0EUNTR?
TC1303B-ZP0EUNTR initiates thermal shutdown at 165°C junction temperature (DS21949C-page 7), with 10°C hysteresis ensuring safe restart only after cooling to ~155°C. Protection is implemented via on-die thermal sensors and disables both regulators until temperature falls below the hysteresis threshold - verified in DS21949C-page 10 temperature specifications and page 19 pin descriptions.
TC1303B-ZP0EUNTR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Topology:
- Step-Down (Buck) Synchronous (1), Linear (LDO) (1)
- Number of Outputs:
- 2
- Frequency - Switching:
- 2MHz
- Voltage/Current - Output 1:
- Adj, 500mA
- Voltage/Current - Output 2:
- 1.8V, 300mA
- Voltage/Current - Output 3:
- -
- w/LED Driver:
- No
- w/Supervisor:
- No
- w/Sequencer:
- Yes
- Voltage - Supply:
- 2.7V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 10-MSOP
TC1303B-ZP0EUNTR FAQ
1.How can I place an order for TC1303B-ZP0EUNTR through Aetrix?
Please submit a Request for Quotation (RFQ) for TC1303B-ZP0EUNTR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TC1303B-ZP0EUNTR reliable?
The price and inventory of TC1303B-ZP0EUNTR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TC1303B-ZP0EUNTR is usually 5 days.
3.What payment methods are accepted for TC1303B-ZP0EUNTR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TC1303B-ZP0EUNTR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TC1303B-ZP0EUNTR?
TC1303B-ZP0EUNTR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TC1303B-ZP0EUNTR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TC1303B-ZP0EUNTR?
For technical support, including TC1303B-ZP0EUNTR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TC1303B-ZP0EUNTR requirements.
6.How does Aetrix verify that TC1303B-ZP0EUNTR is sourced from the original manufacturer or authorized distributors?
All TC1303B-ZP0EUNTR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TC1303B-ZP0EUNTR meets industry standards.
7.What is the process for return or replacement of TC1303B-ZP0EUNTR?
All TC1303B-ZP0EUNTR units undergo pre-shipment inspection (PSI). If there is an issue with TC1303B-ZP0EUNTR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TC1303B-ZP0EUNTR part is unused and in its original packaging.
Return procedure for TC1303B-ZP0EUNTR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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