Microchip Technology TC1303C-VP0EMFTR
- Part No.:
- TC1303C-VP0EMFTR
- Manufacturer:
- Microchip Technology
- Category:
- Voltage Regulators - Linear + Switching
- Package:
- 10-VFDFN Exposed Pad
- Datasheet:
-
TC1303C-VP0EMFTR.pdf
- Description:
- IC REG DL BUCK/LINEAR SYNC 10DFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
TC1303C-VP0EMFTR from Microchip Technology is a dual-output power management IC integrating a 500 mA synchronous buck regulator and a 300 mA low-dropout linear regulator (LDO), with power-good monitoring of both outputs. It delivers 0.8–4.5 V adjustable or fixed buck output (e.g., 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V) and fixed LDO outputs (1.5 V, 1.8 V, 2.5 V, 3.3 V), operates from 2.7–5.5 V input, and features 65 µA typical quiescent current and 300 ms PG delay for processor reset in portable medical instruments.
For engineers reviewing the TC1303C-VP0EMFTR datasheet, TC1303C-VP0EMFTR pinout, TC1303C-VP0EMFTR application, or TC1303C-VP0EMFTR equivalent, key selection criteria include dual-rail sequencing capability, independent shutdown control per rail, 2.0 MHz fixed-frequency PWM operation with automatic PFM transition at light load, 137 mV typical LDO dropout at 200 mA, and open-drain power-good output monitoring both regulators.
Technical Context
The TC1303C-VP0EMFTR implements a synchronous buck topology with integrated high- and low-side MOSFETs (RDS(on) = 450 mΩ each), fixed 2.0 MHz switching frequency under heavy load, and seamless auto-transition to pulse-frequency modulation (PFM) mode below ~10 mA to minimize IQ. Its LDO uses internal compensation and requires only a 1 µF ceramic output capacitor.
Power-good logic monitors regulation status of both VOUT1 and VOUT2 simultaneously with 94% threshold high and 89% threshold low, 2% hysteresis, and 300 ms active timeout period. UVLO triggers at 2.55 V nominal with 200 mV hysteresis, and thermal shutdown activates at 165°C with 10°C hysteresis.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Buck Output Current | 500 mA maximum - supports core voltage rails for ARM Cortex-M microcontrollers or FPGA I/O banks |
| LDO Output Current | 300 mA maximum - powers analog sensors, RF transceivers, or USB PHY circuitry without external pass transistor |
| Quiescent Current | 65 µA typical - enables >1-year battery life in always-on wearable medical devices with 200 mAh Li-ion cell |
| LDO Dropout Voltage | 137 mV typical @ 200 mA - allows 2.5 V LDO output from 2.7 V input, maximizing battery utilization |
| Switching Frequency | 2.0 MHz fixed (heavy load) - permits use of compact 4.7 µH inductor and reduces EMI filtering footprint |
| Power-Good Delay | 300 ms active timeout - meets Intel/ARM reset timing requirements for safe processor initialization |
| Operating Temp Range | −40°C to +125°C junction - qualified for industrial-grade handheld diagnostics equipment |
Pinout & Package
TC1303C-VP0EMFTR is housed in a 10-pin 3×3 mm DFN package with exposed thermal pad (EP), optimized for high-power-density portable designs. Pin 11 (EP) must be soldered to AGND for thermal and electrical integrity.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 SHDN2 | LDO shutdown control | Active-low logic input; <15% VIN disables LDO, >45% VIN enables - enables independent rail control in multi-voltage systems |
| 2 VIN2 | LDO input supply | Accepts 2.7–5.5 V; must be short-traced to VIN1 to minimize noise coupling into analog LDO path |
| 3 VOUT2 | LDO regulated output | Delivers fixed 1.5/1.8/2.5/3.3 V; requires ≥1 µF ceramic capacitor to AGND for stability |
| 4 PG | Power-good indicator | Open-drain output asserting when both VOUT1 and VOUT2 are within ±6% regulation - used for system reset coordination |
| 5 AGND | Analog ground reference | Separate ground return for feedback and error amplifiers; must connect to quiet analog ground plane |
| 6 PGND | Power ground return | High-current return path for buck switch node; requires low-inductance connection to input/output capacitors |
| 7 LX | Buck switch node | Connects to external inductor; carries high di/dt switching current - demands tight layout and Kelvin routing |
| 8 VIN1 | Buck input supply | Accepts 2.7–5.5 V; shares input source with VIN2 per datasheet Note 8 - simplifies single-input dual-rail design |
| 9 SHDN1 | Buck shutdown control | Active-low logic input; independent of SHDN2 - allows staggered startup/shutdown sequences |
| 10 VFB1/VOUT1 | Buck feedback or output | Configurable: connect to divider midpoint for adjustable output (0.8–4.5 V), or directly to VOUT1 for fixed options |
Key Features
| Feature | Design Value |
|---|---|
| Independent shutdown per rail | SHDN1 and SHDN2 enable precise sequencing - e.g., hold LDO active while buck ramps for analog bias before digital core boot |
| Internally compensated LDO | Eliminates need for external compensation network - reduces BOM count and layout complexity for space-constrained PCBs |
| Automatic PWM-to-PFM mode transition | Maintains >85% efficiency down to 100 µA load - critical for ultra-low-power sleep modes in portable health monitors |
| Both outputs monitored by PG | Single open-drain PG signal asserts only when both rails are valid - prevents false resets during transient load events on either rail |
| Overtemperature & short-circuit protection | Thermal shutdown at 165°C with 10°C hysteresis and cycle-by-cycle current limiting - ensures robustness in unventilated enclosures |
Applications
| Portable Medical Diagnostics | USB-Powered Test Equipment |
|---|---|
Use Scenario: Handheld blood glucose meter with LCD display, Bluetooth LE radio, and precision ADC. IC Role / Device Role / Timing Role: Dual-rail PMIC supplying 1.8 V to BLE SoC core and 3.3 V to analog front-end and display driver. Use Value: 65 µA quiescent current extends 200 mAh coin-cell life beyond 18 months; PG assertion coordinates MCU wake-up and sensor calibration sequence. | Use Scenario: Field-deployable oscilloscope probe powered solely via USB 2.0 (5 V @ 500 mA). IC Role / Device Role / Timing Role: Generates 3.3 V for digital logic and 1.2 V for high-speed ADC sampling clock domain. Use Value: 2.0 MHz switching enables <2 mm² inductor footprint; independent SHDN pins allow ADC power-up only during acquisition to minimize noise. |
| Industrial Handheld Terminals | Low-Power IoT Edge Sensors |
Use Scenario: Ruggedized barcode scanner operating across −20°C to +70°C ambient. IC Role / Device Role / Timing Role: Supplies 3.3 V to imager and 1.5 V to microcontroller core, with PG enabling safe firmware update handshake. Use Value: −40°C to +125°C junction rating ensures reliability in cold-storage environments; 137 mV LDO dropout preserves runtime as battery voltage sags. | Use Scenario: Battery-operated environmental sensor node transmitting temperature/humidity via LoRaWAN every 15 minutes. IC Role / Device Role / Timing Role: Powers 3.3 V LoRa transceiver and 1.8 V ultra-low-power MCU, entering deep-sleep with both rails disabled. Use Value: 0.05 µA shutdown current minimizes annual self-discharge; automatic PFM mode maintains >90% efficiency at 50 µA sleep current. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-output PMIC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS65023BRSBR | Triple-output (2 buck + 1 LDO), 2.25 MHz switching, 85 µA IQ, no independent LDO shutdown | Supports additional voltage rail; lacks per-rail enable control needed for strict sequencing | Select when third rail required and sequencing flexibility is secondary to integration density |
| RT8059ZSP | Dual buck only (no integrated LDO), 3 MHz switching, 30 µA IQ, 1.2–3.3 V adjustable outputs | Requires external LDO for clean analog rail; better suited for digital-only multi-core SoCs | Select when lowest possible IQ is critical and analog subsystem uses separate low-noise LDO |
Compared with TPS65023BRSBR and RT8059ZSP, the TC1303C-VP0EMFTR uniquely combines independent buck/LDO shutdown, dual-rail PG monitoring, and sub-100 µA quiescent current in a 3×3 mm DFN - making it optimal for space- and battery-limited portable medical and industrial handhelds where rail sequencing and reset coordination are mandatory.
Availability
TC1303C-VP0EMFTR is available at Aetrix Electronics and suitable for portable medical diagnostics, USB-powered test equipment, and industrial handheld terminals requiring stable component supply across extended product lifecycles.
Supply support for TC1303C-VP0EMFTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a leading provider of microcontrollers, analog components, and power management ICs, serving automotive, industrial, and consumer markets with high-reliability silicon solutions.
The TC1303 family was designed specifically for battery-powered portable electronics needing compact, efficient dual-rail power conversion with precise reset signaling - targeting cellular phones, PDAs, and handheld medical instruments.
FAQ
What output voltages does the TC1303C-VP0EMFTR support?
The TC1303C-VP0EMFTR supports adjustable buck output from 0.8 V to 4.5 V (via external resistor divider on VFB1) and fixed buck outputs of 0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, or 3.3 V. The LDO provides fixed outputs of 1.5 V, 1.8 V, 2.5 V, or 3.3 V. The specific configuration of TC1303C-VP0EMFTR is factory-set; its part number suffix "VP0E" indicates 3.3 V buck and 1.8 V LDO outputs.
How does the power-good (PG) function operate in TC1303C-VP0EMFTR?
In TC1303C-VP0EMFTR, the PG pin is an open-drain output that asserts low only when both VOUT1 and VOUT2 are within 94% to 96% of their nominal values. It includes a 300 ms active timeout period after regulation is achieved and features 2% hysteresis to prevent chatter during marginal conditions. This dual-rail monitoring ensures reliable processor reset coordination.
Can TC1303C-VP0EMFTR operate from a single 3.7 V Li-ion battery?
Yes. TC1303C-VP0EMFTR operates from 2.7 V to 5.5 V input, fully covering the 4.2 V (fully charged) to 2.8 V (discharged) range of a single-cell Li-ion battery. Its 137 mV typical LDO dropout at 200 mA allows sustained 1.8 V LDO output even at battery voltages as low as 2.9 V, extending usable runtime.
What is the thermal performance of TC1303C-VP0EMFTR in the 3×3 mm DFN package?
In the 10-lead 3×3 mm DFN package with exposed pad soldered to AGND, TC1303C-VP0EMFTR has a typical junction-to-ambient thermal resistance (θJA) of 41°C/W on a 4-layer board with internal ground plane and two thermal vias. This enables full 500 mA buck and 300 mA LDO output capability up to +85°C ambient without derating, provided proper PCB copper area is allocated.
Does TC1303C-VP0EMFTR require external compensation components?
No. Both the synchronous buck regulator and the LDO in TC1303C-VP0EMFTR are internally compensated. The buck requires only an external inductor and input/output capacitors; the LDO requires only a 1 µF ceramic output capacitor on VOUT2. No external RC networks or compensation pins are needed, simplifying design and reducing bill-of-materials cost.
TC1303C-VP0EMFTR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 10-VFDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Topology:
- Step-Down (Buck) Synchronous (1), Linear (LDO) (1)
- Number of Outputs:
- 2
- Frequency - Switching:
- 2MHz
- Voltage/Current - Output 1:
- 1.2V, 500mA
- Voltage/Current - Output 2:
- 1.8V, 300mA
- Voltage/Current - Output 3:
- -
- w/LED Driver:
- No
- w/Supervisor:
- No
- w/Sequencer:
- Yes
- Voltage - Supply:
- 2.7V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 10-DFN (3x3)
TC1303C-VP0EMFTR FAQ
1.How can I place an order for TC1303C-VP0EMFTR through Aetrix?
Please submit a Request for Quotation (RFQ) for TC1303C-VP0EMFTR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TC1303C-VP0EMFTR reliable?
The price and inventory of TC1303C-VP0EMFTR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TC1303C-VP0EMFTR is usually 5 days.
3.What payment methods are accepted for TC1303C-VP0EMFTR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TC1303C-VP0EMFTR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TC1303C-VP0EMFTR?
TC1303C-VP0EMFTR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TC1303C-VP0EMFTR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TC1303C-VP0EMFTR?
For technical support, including TC1303C-VP0EMFTR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TC1303C-VP0EMFTR requirements.
6.How does Aetrix verify that TC1303C-VP0EMFTR is sourced from the original manufacturer or authorized distributors?
All TC1303C-VP0EMFTR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TC1303C-VP0EMFTR meets industry standards.
7.What is the process for return or replacement of TC1303C-VP0EMFTR?
All TC1303C-VP0EMFTR units undergo pre-shipment inspection (PSI). If there is an issue with TC1303C-VP0EMFTR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TC1303C-VP0EMFTR part is unused and in its original packaging.
Return procedure for TC1303C-VP0EMFTR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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