My Inquiry
My Account
Microchip Technology TC1303C-VP0EUN
- Part No.:
- TC1303C-VP0EUN
- Manufacturer:
- Microchip Technology
- Category:
- Voltage Regulators - Linear + Switching
- Package:
- 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
- Datasheet:
-
TC1303C-VP0EUN.pdf
- Description:
- IC REG DL BUCK/LNR SYNC 10MSOP
- Quantity:
- Payment:
- Shipping:
Inventory:4,888
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
TC1303C-VP0EUN from Microchip Technology is a dual-output power management IC integrating a 500 mA synchronous buck regulator and a 300 mA low-dropout linear regulator (LDO), with power-good monitoring of both outputs. It delivers 1.8 V @ 500 mA (buck) and 3.3 V @ 300 mA (LDO) from a 2.7–5.5 V input, features 65 µA typical quiescent current, 2.0 MHz fixed-frequency PWM operation, and operates across –40°C to +125°C junction temperature for portable medical instruments and USB-powered devices.
For engineers reviewing the TC1303C-VP0EUN datasheet, TC1303C-VP0EUN pinout, TC1303C-VP0EUN application, or TC1303C-VP0EUN equivalent, key selection criteria include independent shutdown control per rail, 137 mV LDO dropout at 200 mA, open-drain PG output with 300 ms delay, internal compensation, and compatibility with 1 µF ceramic output capacitors on both rails.
Technical Context
The TC1303C-VP0EUN implements a synchronous buck stage with PFM/PWM auto-transition for light/heavy load efficiency optimization, and a separate LDO stage with internal reference and feedback loop. Its power-good circuit monitors regulation status of both VOUT1 and VOUT2 simultaneously - a distinguishing feature versus TC1303A (buck-only monitoring) and TC1303B (LDO-only monitoring).
Shutdown logic is decoupled: SHDN1 controls the buck regulator only, while SHDN2 independently disables the LDO. The device uses internal compensation for both regulators, eliminating external compensation components, and integrates overtemperature, UVLO, and short-circuit protection on both outputs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Buck Output Current | 500 mA max - supports core voltage rails for low-power processors and FPGAs without external current boosting. |
| LDO Output Current | 300 mA max - powers I/O, sensors, or RF sections requiring low-noise bias with minimal board area. |
| Quiescent Current | 65 µA typical - enables >1-year battery life in always-on portable medical or IoT edge nodes. |
| Switching Frequency | 2.0 MHz fixed - allows use of compact 4.7 µH inductors and reduces EMI filtering footprint. |
| LDO Dropout Voltage | 137 mV @ 200 mA - ensures stable 3.3 V output even when input drops to 3.437 V, critical for Li-ion discharge profiles. |
| Power-Good Monitoring | Monitors both VOUT1 and VOUT2 - provides single reset signal valid only when *both* rails are within ±2.5% tolerance, preventing partial-power-up failures. |
| Operating Temperature | –40°C to +125°C junction - qualified for under-hood automotive auxiliary modules and industrial handhelds. |
Pinout & Package
TC1303C-VP0EUN is housed in a 10-pin 3×3 mm DFN package with exposed thermal pad (EP), optimized for high thermal conductivity and space-constrained PCB layouts. Pin 1 is SHDN2 (LDO shutdown), pin 10 is PG (open-drain power-good), and the EP must be soldered to AGND for thermal and electrical integrity.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| SHDN2 (Pin 1) | LDO enable control | Active-high logic input (>45% VIN); independent of buck regulator - enables staggered power sequencing or LDO-only standby mode. |
| VIN2 (Pin 2) | LDO input supply | Accepts same 2.7–5.5 V input as VIN1; requires short trace routing to VIN1 to minimize noise coupling into LDO path. |
| VOUT2 (Pin 3) | LDO regulated output | Delivers fixed 3.3 V (per VP0EUN suffix); requires ≥1 µF ceramic capacitor to AGND for stability and transient response. |
| PG (Pin 4) | Power-good indicator | Open-drain output asserting low when *both* VOUT1 and VOUT2 are within 94–96% of nominal - used to release processor reset. |
| AGND (Pin 5) | Analog ground reference | Must connect to clean analog ground plane; separates noise-sensitive feedback paths from PGND return currents. |
| PGND (Pin 6) | Power ground return | High-current return path for buck switch node (LX); routed separately from AGND to avoid ground bounce on feedback pins. |
| LX (Pin 7) | Buck switch node | Connects to external inductor; carries high di/dt switching current - requires tight layout with minimal loop area to reduce EMI. |
| VIN1 (Pin 8) | Buck input supply | Main input for buck stage; shares same source as VIN2 but routed with low-impedance path to support 500 mA peak current. |
| SHDN1 (Pin 9) | Buck enable control | Active-high logic input (>45% VIN); independent of SHDN2 - allows buck-only disable during LDO-powered sleep states. |
| VFB1/VOUT1 (Pin 10) | Buck feedback/sense | Configured as VOUT1 for fixed-output variants (e.g., VP0EUN = 1.8 V); connects directly to buck output for regulation without external divider. |
Key Features
| Feature | Design Value |
|---|---|
| Independent shutdown per regulator | Enables flexible power sequencing: e.g., keep LDO active for real-time clock while shutting down buck during deep sleep. |
| Internal compensation | Eliminates need for external compensation networks on either regulator - reduces BOM count and layout complexity. |
| 2.0 MHz PWM + auto PFM transition | Maintains >90% efficiency at full load while dropping quiescent current to ~38 µA in light-load PFM mode. |
| 1 µF LDO output capacitor support | Reduces required board area by >50% vs. legacy LDOs needing ≥10 µF tantalum - improves reliability and cost. |
| Open-drain PG with dual-rail monitoring | Ensures system reset is held until *both* 1.8 V core and 3.3 V I/O rails are fully stabilized - prevents firmware corruption. |
Applications
| Portable Medical Sensors | USB-Powered Test Equipment |
|---|---|
Use Scenario: Battery-operated glucose meter with LCD display and Bluetooth LE radio. IC Role / Device Role / Timing Role: Dual-rail power manager supplying 1.8 V to MCU core and 3.3 V to display driver/RF transceiver. Use Value: 65 µA quiescent current extends CR2032 battery life beyond 18 months; PG output synchronizes MCU boot with full rail stabilization. | Use Scenario: Handheld oscilloscope powered solely via USB 2.0 (5 V @ 500 mA). IC Role / Device Role / Timing Role: Primary voltage translator generating 1.8 V analog front-end bias and 3.3 V digital logic supply. Use Value: 2.0 MHz switching enables compact 4.7 µH inductor; 137 mV LDO dropout ensures 3.3 V remains stable as USB input sags to 4.4 V. |
| Industrial Handheld Terminals | Low-Power Edge AI Modules |
Use Scenario: Ruggedized barcode scanner with cold-temperature operation requirement. IC Role / Device Role / Timing Role: Power source for ARM Cortex-M7 MCU (1.8 V), image sensor (3.3 V), and EEPROM interface. Use Value: –40°C to +125°C rating guarantees startup and regulation in freezer warehouses; independent SHDN1/SHDN2 supports sensor wake-on-barcode. | Use Scenario: TinyML inference node using ultra-low-power microcontroller and MEMS microphone. IC Role / Device Role / Timing Role: Efficient dual-rail supply enabling simultaneous CPU execution and analog signal conditioning. Use Value: Auto PFM mode cuts idle current to <40 µA; dual PG monitoring prevents neural net initialization before both rails settle within tolerance. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-output PMIC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS65023BRSAT | Triple-output (2 buck + 1 LDO), higher IQ (100 µA), 3.0 MHz switching, QFN-24 package | Supports additional 1.2 V rail for DDR termination; larger footprint and higher cost | Select when third regulated rail or higher switching frequency is required; not drop-in due to pin count and package mismatch. |
| RT8059ZSP | Dual buck (no LDO), 1.5 MHz, 60 µA IQ, WDFN-10 package, no PG monitoring | Lacks LDO output and dual-rail PG - unsuitable where low-noise bias or coordinated reset is mandatory | Consider only if both rails can be switched; requires external LDO and reset supervisor for equivalent functionality. |
Compared with TPS65023BRSAT and RT8059ZSP, TC1303C-VP0EUN uniquely combines buck+LDO integration, dual-rail PG monitoring, and 3×3 mm DFN packaging in a single 10-pin solution - offering optimal balance of size, intelligence, and cost for space-constrained dual-rail systems.
Availability
TC1303C-VP0EUN is available at Aetrix Electronics and suitable for portable medical instruments, USB-powered test equipment, and industrial handheld terminals requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for TC1303C-VP0EUN includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a leading provider of microcontrollers, analog, FPGA, and power management solutions, serving automotive, industrial, and consumer markets with high-reliability silicon and development tools.
The TC1303 family targets battery-powered and USB-fed portable electronics, delivering integrated dual-rail power conversion with minimal external components and robust protection features for reliable field operation.
FAQ
What output voltages does the TC1303C-VP0EUN provide?
The TC1303C-VP0EUN provides a fixed 1.8 V output from its synchronous buck regulator (VOUT1) and a fixed 3.3 V output from its low-dropout linear regulator (VOUT2). These values are encoded in the part suffix "VP0EUN", where "VP" denotes 1.8 V buck and "0EUN" specifies 3.3 V LDO. Both outputs are internally compensated and require no external feedback resistors.
How does the power-good (PG) function operate on the TC1303C-VP0EUN?
The TC1303C-VP0EUN's PG pin is an open-drain output that asserts low only when *both* VOUT1 and VOUT2 are within 94–96% of their nominal values. It includes a built-in 300 ms delay after regulation is achieved, making it suitable for processor reset timing. This dual-rail monitoring distinguishes TC1303C-VP0EUN from TC1303A (buck-only PG) and TC1303B (LDO-only PG).
Can the TC1303C-VP0EUN operate from a single 3.7 V Li-ion cell?
Yes - the TC1303C-VP0EUN supports input voltages from 2.7 V to 5.5 V, covering the full discharge curve of a single-cell Li-ion (3.0–4.2 V). Its 137 mV LDO dropout ensures the 3.3 V output remains regulated down to VIN2 = 3.437 V, and its buck stage maintains >90% efficiency at 3.7 V input with 1.8 V output.
What is the thermal performance of the TC1303C-VP0EUN in its DFN package?
In a typical 4-layer PCB with internal ground plane and two vias under the exposed pad, the TC1303C-VP0EUN (10L-DFN) has a junction-to-ambient thermal resistance (θJA) of 41°C/W. At maximum 500 mA buck + 300 mA LDO load and 25°C ambient, junction temperature rise is ~33°C - well within the –40°C to +125°C operating range, assuming proper EP-to-AGND soldering.
Does the TC1303C-VP0EUN require external compensation components?
No - both the buck regulator and LDO in the TC1303C-VP0EUN are internally compensated. This eliminates external compensation capacitors and resistors, reducing bill-of-materials cost and PCB area. The design achieves stable regulation across all load and line conditions specified in the DS21949C datasheet without user-adjusted loop tuning.
TC1303C-VP0EUN Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Topology:
- Step-Down (Buck) Synchronous (1), Linear (LDO) (1)
- Number of Outputs:
- 2
- Frequency - Switching:
- 2MHz
- Voltage/Current - Output 1:
- 1.2V, 500mA
- Voltage/Current - Output 2:
- 1.8V, 300mA
- Voltage/Current - Output 3:
- -
- w/LED Driver:
- No
- w/Supervisor:
- No
- w/Sequencer:
- Yes
- Voltage - Supply:
- 2.7V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 10-MSOP
TC1303C-VP0EUN FAQ
1.How can I place an order for TC1303C-VP0EUN through Aetrix?
Please submit a Request for Quotation (RFQ) for TC1303C-VP0EUN on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TC1303C-VP0EUN reliable?
The price and inventory of TC1303C-VP0EUN are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TC1303C-VP0EUN is usually 5 days.
3.What payment methods are accepted for TC1303C-VP0EUN?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TC1303C-VP0EUN transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TC1303C-VP0EUN?
TC1303C-VP0EUN orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TC1303C-VP0EUN order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TC1303C-VP0EUN?
For technical support, including TC1303C-VP0EUN datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TC1303C-VP0EUN requirements.
6.How does Aetrix verify that TC1303C-VP0EUN is sourced from the original manufacturer or authorized distributors?
All TC1303C-VP0EUN products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TC1303C-VP0EUN meets industry standards.
7.What is the process for return or replacement of TC1303C-VP0EUN?
All TC1303C-VP0EUN units undergo pre-shipment inspection (PSI). If there is an issue with TC1303C-VP0EUN, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TC1303C-VP0EUN part is unused and in its original packaging.
Return procedure for TC1303C-VP0EUN:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
TC1303C-VP0EUN Tags
-
TPS6521905RHBR
Texas Instruments
-
MIC3385YHL-TR
Microchip Technology
-
A4402ELPTR-T
Allegro MicroSystems
-
LM26480SQ-AA/NOPB
Texas Instruments
-
A4402KLPTR-T
Allegro MicroSystems
-
BD71847AMWV-E2
ROHM Semiconductor
-
ADP5040ACPZ-1-R7
Analog Devices Inc.
-
LT3048IDC#TRPBF
Analog Devices Inc.
-
ADP5037ACPZ-R7
Analog Devices Inc.
-
XRP7714ILB-F
MaxLinear, Inc.
-
LTC3260EDE#TRPBF
Analog Devices Inc.
-
LTC3260EMSE#PBF
Analog Devices Inc.
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
