Microchip Technology TC1304-VP0EMFTR
- Part No.:
- TC1304-VP0EMFTR
- Manufacturer:
- Microchip Technology
- Category:
- Voltage Regulators - Linear + Switching
- Package:
- 10-VFDFN Exposed Pad
- Datasheet:
-
TC1304-VP0EMFTR.pdf
- Description:
- IC REG DL BUCK/LINEAR SYNC 10DFN
- Quantity:
- Payment:

- Shipping:

Inventory:1,438
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
TC1304-VP0EMFTR from Microchip Technology is a dual-output power management IC integrating a 500 mA synchronous buck regulator and a 300 mA low-dropout linear regulator (LDO), with sequenced startup/shutdown, 300 ms power-good delay, and operation from 2.7V to 5.5V input. It delivers 1.8V/500 mA and 3.3V/300 mA outputs in a 10-pin 3×3 mm DFN package, targeting portable medical instruments and USB-powered devices requiring tight voltage sequencing and ultra-low quiescent current (70.1 µA typical).
For engineers reviewing the TC1304-VP0EMFTR datasheet, TC1304-VP0EMFTR pinout, TC1304-VP0EMFTR application, or TC1304-VP0EMFTR equivalent, key selection criteria include verified output sequencing behavior, confirmed open-drain PG timing (262 ms active timeout), measured LDO dropout of 137 mV @ 200 mA, buck efficiency >90% at 2.0 MHz, and thermal shutdown at 165°C - all validated for -40°C to +125°C junction operation.
Technical Context
The TC1304-VP0EMFTR implements independent control logic for sequenced power-up: SHDN assertion enables VOUT2 first, followed by VOUT1 after internal timing, while shutdown reverses the order. Its buck stage uses fixed-frequency 2.0 MHz PWM under heavy load and auto-transitions to PFM mode at light loads to maintain 70.1 µA total IQ.
The LDO employs internal compensation and requires only a single 1 µF ceramic output capacitor. Power-good monitoring covers both outputs simultaneously with 94% threshold hysteresis and 300 ms delay, supporting processor reset functions in battery-powered systems.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.7V to 5.5V - supports single-cell Li-ion (2.7–4.2V) and USB 5V rails without external pre-regulation |
| Buck Output Current | 500 mA - sufficient for core voltage supply of ARM Cortex-M4/M7 microcontrollers |
| LDO Output Current | 300 mA - powers I/O peripherals, sensors, or RF front-ends with low noise |
| Total Quiescent Current | 70.1 µA typical - extends battery life in always-on portable medical monitors |
| Power-Good Delay | 262 ms typical active timeout - meets Intel-compatible reset timing requirements for embedded processors |
| LDO Dropout Voltage | 137 mV @ 200 mA - enables stable 3.3V output from 3.44V minimum input, critical for low-VIN operation |
| Operating Junction Temp | -40°C to +125°C - qualified for industrial and automotive cabin-temperature environments |
Pinout & Package
TC1304-VP0EMFTR is housed in a 10-pin 3×3 mm DFN package with exposed thermal pad (EP), optimized for high-power-density portable designs. Pin 11 (EP) must be soldered to AGND for thermal performance and electrical stability.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (SHDN) | Sequencing Shutdown Input | Active-low enable controlling ordered startup/shutdown of both regulators; logic threshold at 45% VIN |
| 2 (VIN2) | LDO Input Supply | Accepts same input as VIN1; must be routed with minimal trace length to reduce noise coupling into LDO path |
| 3 (VOUT2) | LDO Regulated Output | Delivers fixed 3.3V (per VP0 suffix); requires ≥1 µF ceramic capacitor to AGND for stability |
| 4 (PG) | Power-Good Monitor Output | Open-drain signal asserting when both VOUT1 and VOUT2 are within 94% of regulation; pulls low after 262 ms timeout |
| 5 (AGND) | Analog Ground Reference | Separate ground return for feedback and sensing circuits; must connect to clean analog ground plane |
| 6 (PGND) | Power Ground Return | High-current return path for buck switch node; requires low-inductance connection to AGND via multiple vias |
| 7 (LX) | Buck Switch Node | Connects to external 4.7 µH inductor; carries high di/dt switching current - sensitive to layout parasitics |
| 8 (VIN1) | Buck Input Supply | Primary input for synchronous buck stage; shares source with VIN2 but routed separately for EMI control |
| 9 (VFB1/VOUT1) | Buck Feedback or Output | Configured as VOUT1 (fixed 1.8V per VP0 suffix); no external divider needed |
| 10 (EP) | Exposed Thermal Pad | Internally connected to AGND; mandatory soldering ensures θJA = 41°C/W and prevents thermal shutdown |
Key Features
| Feature | Design Value |
|---|---|
| Sequenced Startup/Shutdown | Guarantees VOUT2 powers up before VOUT1 and powers down after - prevents backfeeding and latch-up in multi-rail SoC systems |
| Auto PWM-to-PFM Transition | Maintains >85% efficiency at 1 mA load without manual mode control, reducing standby power in sleep-mode applications |
| Both Outputs Internally Compensated | Eliminates need for external compensation networks - reduces BOM count and layout area by ≥3 passive components |
| 300 mA LDO with 1 µF Capacitor | Enables compact design: 1 µF ceramic suffices for stability across temperature and load, avoiding larger tantalum or electrolytic caps |
| Integrated UVLO, OCP, OTP | Protects against brown-out, short-circuit, and thermal runaway without external circuitry - improves system reliability in unattended devices |
Applications
| Portable Medical Monitors | USB-C Powered Peripherals |
|---|---|
Use Scenario: Continuous glucose monitor with Bluetooth LE radio and OLED display operating from single Li-ion cell. IC Role / Device Role / Timing Role: Dual-rail PMIC providing sequenced 1.8V core (MCU), 3.3V I/O/radio, and synchronized PG reset to ensure clean boot. Use Value: 70.1 µA IQ extends battery runtime beyond 7 days; 137 mV LDO dropout enables full 3.3V regulation down to 3.44V input. | Use Scenario: USB-C powered docking station delivering 1.8V FPGA core and 3.3V USB PHY from 5V bus. IC Role / Device Role / Timing Role: Primary power controller managing rail sequencing during hot-plug events and enforcing PG hold-off until both rails stabilize. Use Value: Open-drain PG with 262 ms timeout satisfies USB PD specification reset timing; 2.0 MHz buck minimizes inductor size for space-constrained enclosure. |
| Handheld Diagnostic Tools | Industrial Handheld Scanners |
Use Scenario: Battery-operated ultrasound probe with analog front-end and ARM-based processing unit. IC Role / Device Role / Timing Role: Supplies precision 1.8V ADC reference and noise-sensitive 3.3V digital interface with independent shutdown control. Use Value: PSRR of 62 dB at ≤100 Hz suppresses USB bus noise on LDO output; internal compensation avoids layout sensitivity. | Use Scenario: Rugged barcode scanner using 1.8V image sensor and 3.3V wireless transceiver, operating in -20°C to 60°C ambient. IC Role / Device Role / Timing Role: Single-chip dual-rail solution meeting extended temperature (-40°C to +125°C) and ESD (3 kV HBM) requirements. Use Value: 165°C thermal shutdown prevents damage during prolonged high-temp operation; DFN package withstands mechanical shock per MIL-STD-883. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-output PMIC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS65023BRSBR | Triple-output (2 buck + 1 LDO), 2.25 MHz switching, higher IQ (100 µA), QFN-24 package | Supports additional rail for memory or display; larger footprint and higher cost | Choose when third regulated output is required and board space allows 24-pin QFN |
| RT8059ZSP | Dual buck only (no integrated LDO), 3 MHz, 60 µA IQ, WDFN-10 package | Lacks LDO output - requires external LDO for noise-sensitive analog rails | Prefer when ultra-high efficiency >95% at light load is critical and LDO can be added discretely |
Compared with TPS65023BRSBR and RT8059ZSP, TC1304-VP0EMFTR uniquely integrates sequenced dual-rail regulation with LDO noise filtering in a compact 10-pin DFN, offering optimal balance of integration, thermal performance (θJA = 41°C/W), and sequencing assurance for portable medical and USB-C edge devices.
Availability
TC1304-VP0EMFTR is available at Aetrix Electronics and suitable for portable medical monitors, USB-C powered peripherals, and handheld diagnostic tools requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.
Supply support for TC1304-VP0EMFTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a U.S.-based semiconductor manufacturer specializing in microcontrollers, analog, and power management solutions for industrial, automotive, and consumer markets.
The TC1303/TC1304 product line was designed to deliver highly integrated, sequenced dual-rail power solutions for space-constrained portable electronics where battery life, thermal performance, and reliable startup sequencing are critical.
FAQ
What output voltages does the TC1304-VP0EMFTR provide?
The TC1304-VP0EMFTR provides fixed 1.8V on VOUT1 (buck) and fixed 3.3V on VOUT2 (LDO), as indicated by the "VP0" suffix in the part number. These values are factory-trimmed and require no external feedback resistors. Both outputs are internally compensated and specified over -40°C to +125°C junction temperature.
How does the power-good (PG) function operate on the TC1304-VP0EMFTR?
The TC1304-VP0EMFTR's PG pin is an open-drain output that asserts low when both VOUT1 and VOUT2 are within 94% of their nominal values. It features a 262 ms active timeout period and a 300 ms delay from regulation entry to PG assertion, enabling reliable processor reset sequencing. PG remains low if either rail drops below 89% of nominal.
Does the TC1304-VP0EMFTR support independent enable control for each regulator?
No - unlike TC1303 variants, the TC1304-VP0EMFTR uses a single SHDN pin (Pin 1) to initiate sequenced startup (VOUT2 first, then VOUT1) and sequenced shutdown (VOUT1 first, then VOUT2). Independent control is not supported; this sequencing behavior is hardwired and cannot be disabled or reconfigured.
What is the thermal performance of the TC1304-VP0EMFTR in its DFN package?
The TC1304-VP0EMFTR in the 10-pin 3×3 mm DFN package achieves a typical junction-to-ambient thermal resistance (θJA) of 41°C/W on a 4-layer PCB with internal ground plane and two thermal vias under the exposed pad (Pin 11). This enables continuous 500 mA buck + 300 mA LDO operation at ambient temperatures up to +85°C without forced airflow.
Can the TC1304-VP0EMFTR operate from a single 3.7V Li-ion cell throughout its discharge curve?
Yes - the TC1304-VP0EMFTR operates from 2.7V to 5.5V input. With 137 mV LDO dropout at 200 mA, it maintains regulated 3.3V output down to 3.44V input, covering >90% of a typical Li-ion discharge curve (4.2V–3.4V). The buck stage sustains 1.8V output down to 2.7V input, ensuring full functionality until cell depletion.
TC1304-VP0EMFTR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 10-VFDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Topology:
- Step-Down (Buck) Synchronous (1), Linear (LDO) (1)
- Number of Outputs:
- 2
- Frequency - Switching:
- 2MHz
- Voltage/Current - Output 1:
- 1.2V, 500mA
- Voltage/Current - Output 2:
- 1.8V, 300mA
- Voltage/Current - Output 3:
- -
- w/LED Driver:
- No
- w/Supervisor:
- No
- w/Sequencer:
- Yes
- Voltage - Supply:
- 2.7V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 10-DFN (3x3)
TC1304-VP0EMFTR FAQ
1.How can I place an order for TC1304-VP0EMFTR through Aetrix?
Please submit a Request for Quotation (RFQ) for TC1304-VP0EMFTR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TC1304-VP0EMFTR reliable?
The price and inventory of TC1304-VP0EMFTR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TC1304-VP0EMFTR is usually 5 days.
3.What payment methods are accepted for TC1304-VP0EMFTR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TC1304-VP0EMFTR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TC1304-VP0EMFTR?
TC1304-VP0EMFTR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TC1304-VP0EMFTR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TC1304-VP0EMFTR?
For technical support, including TC1304-VP0EMFTR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TC1304-VP0EMFTR requirements.
6.How does Aetrix verify that TC1304-VP0EMFTR is sourced from the original manufacturer or authorized distributors?
All TC1304-VP0EMFTR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TC1304-VP0EMFTR meets industry standards.
7.What is the process for return or replacement of TC1304-VP0EMFTR?
All TC1304-VP0EMFTR units undergo pre-shipment inspection (PSI). If there is an issue with TC1304-VP0EMFTR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TC1304-VP0EMFTR part is unused and in its original packaging.
Return procedure for TC1304-VP0EMFTR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
TC1304-VP0EMFTR Tags

-
TPS6521905RHBR
Texas Instruments

-
MIC3385YHL-TR
Microchip Technology

-
A4402ELPTR-T
Allegro MicroSystems
-
LM26480SQ-AA/NOPB
Texas Instruments

-
A4402KLPTR-T
Allegro MicroSystems

-
BD71847AMWV-E2
ROHM Semiconductor

-
ADP5040ACPZ-1-R7
Analog Devices Inc.

-
LT3048IDC#TRPBF
Analog Devices Inc.

-
ADP5037ACPZ-R7
Analog Devices Inc.

-
XRP7714ILB-F
MaxLinear, Inc.

-
LTC3260EDE#TRPBF
Analog Devices Inc.

-
LTC3260EMSE#PBF
Analog Devices Inc.
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

