Microchip Technology TC1304-ZP0EMF
- Part No.:
- TC1304-ZP0EMF
- Manufacturer:
- Microchip Technology
- Category:
- Voltage Regulators - Linear + Switching
- Package:
- 10-VFDFN Exposed Pad
- Datasheet:
-
TC1304-ZP0EMF.pdf
- Description:
- IC REG DL BUCK/LINEAR SYNC 10DFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
TC1304-ZP0EMF from Microchip Technology is a dual-output power management IC integrating a 500 mA synchronous buck regulator and a 300 mA low-dropout linear regulator (LDO), with sequenced startup/shutdown, 300 ms power-good delay, and total quiescent current of 70.1 µA typical. It operates across -40°C to +125°C and supports input voltages from 2.7 V to 5.5 V, serving as a compact voltage source for battery-powered portable electronics requiring precise core and bias rail sequencing.
For engineers reviewing the TC1304-ZP0EMF datasheet, TC1304-ZP0EMF pinout, TC1304-ZP0EMF application, or TC1304-ZP0EMF equivalent, key selection considerations include its dual-regulator architecture with independent output monitoring, fixed 2.0 MHz switching frequency, 137 mV LDO dropout at 200 mA, open-drain PG output, and support for both adjustable (0.8–4.5 V) and fixed-output configurations in a 10-pin DFN package.
Technical Context
The TC1304-ZP0EMF implements sequenced power-up and power-down control: the LDO output (VOUT2) ramps first, followed by the buck output (VOUT1), ensuring safe biasing of downstream logic before core voltage application. Its buck stage uses synchronous rectification with P- and N-channel MOSFETs (RDS(on) = 450 mΩ each), fixed 2.0 MHz PWM operation under heavy load, and automatic transition to PFM mode at light loads to maintain ultra-low IQ.
The LDO output features internal compensation, requires only a 1 µF ceramic capacitor, and delivers ±0.3% output voltage tolerance over temperature and line/load variations. The open-drain PG signal monitors both outputs simultaneously and asserts after a 300 ms delay once both VOUT1 and VOUT2 reach ≥94% of regulation - a timing-critical function for processor reset coordination.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.7 V to 5.5 V - supports single-cell Li-ion (2.7–4.2 V) and USB 5 V supply without external pre-regulation |
| Buck Output Current | 500 mA - sufficient for powering ARM Cortex-M cores or FPGA I/O banks at 1.2–1.8 V |
| LDO Output Current | 300 mA - enables clean auxiliary rails for analog sensors or communication interfaces |
| Quiescent Current | 70.1 µA typical - extends battery life in always-on subsystems such as real-time clocks or wake-on-event circuits |
| LDO Dropout Voltage | 137 mV @ 200 mA - allows operation with minimal headroom, e.g., 3.3 V output from 3.44 V input |
| Switching Frequency | 2.0 MHz (fixed) - permits use of small 4.7 µH inductors and reduces EMI filtering burden |
| Operating Temperature | -40°C to +125°C junction - qualified for industrial and automotive under-hood applications |
Pinout & Package
TC1304-ZP0EMF is housed in a 3×3 mm, 10-pin DFN package with exposed thermal pad (EP), optimized for high-power-density PCB layouts and thermal performance (θJA = 41°C/W on 4-layer board). Pin functions are electrically and physically identical to the MSOP variant but with tighter footprint and improved thermal dissipation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 - SHDN | Global shutdown input | Active-high logic input (>45% VIN) initiating controlled sequencing: LDO powers up/down before buck regulator |
| 2 - VIN2 | LDO input supply | Accepts same input as VIN1; must be routed with minimal trace length to reduce noise coupling into LDO path |
| 3 - VOUT2 | LDO regulated output | Delivers 300 mA with ≤137 mV dropout; requires ≥1 µF ceramic capacitor to AGND for stability |
| 4 - PG | Power-good monitor output | Open-drain signal asserting after 300 ms when both VOUT1 and VOUT2 are within 94% of target - used for processor reset hold-off |
| 5 - AGND | Analog ground reference | Must be connected to quiet analog ground plane; separate from PGND to minimize switching noise injection into LDO feedback |
| 6 - PGND | Power ground return | High-current return path for buck switch node (LX); requires low-inductance connection to input/output capacitors |
| 7 - LX | Buck switch node | Connects to external inductor; carries high di/dt pulses - layout critical to minimize EMI and voltage spikes |
| 8 - VIN1 | Buck input supply | Primary input for synchronous buck stage; shares input source with VIN2 per design note |
| 9 - VFB1/VOUT1 | Buck feedback or output | Configurable: for adjustable mode, connects to resistor divider; for fixed-output variants, directly ties to VOUT1 |
| 10 - EP | Exposed thermal pad | Internally connected to AGND; must be soldered to large copper pour for thermal conduction and EMI shielding |
Key Features
| Feature | Design Value |
|---|---|
| Sequenced startup/shutdown | Guarantees LDO (VOUT2) powers up before buck (VOUT1), preventing backfeeding and enabling safe SoC boot sequence |
| Both outputs internally compensated | Eliminates need for external compensation networks - reduces BOM count and layout complexity |
| Automatic PWM-to-PFM mode transition | Maintains >85% efficiency at light loads (<10 mA) while holding IQ below 70.1 µA - critical for standby power budgets |
| Overtemperature and short-circuit protection | Thermal shutdown triggers at 165°C with 10°C hysteresis; LDO short-circuit current limited to 240 mA average - ensures robust field reliability |
| UVLO with 200 mV hysteresis | Prevents erratic operation during brown-out; releases regulation only when VIN rises 200 mV above 2.55 V threshold |
Applications
| Portable Medical Devices | USB-Powered Test Equipment |
|---|---|
Use Scenario: Handheld blood glucose meters and pulse oximeters operating from single-cell lithium batteries with strict low-power sleep requirements. IC Role / Device Role / Timing Role: Dual-rail power source delivering 1.8 V (core MCU) and 3.3 V (sensor interface/ADC) with sequenced enable and PG-controlled system reset. Use Value: 70.1 µA total IQ extends battery life beyond 1 year in sleep mode; 137 mV LDO dropout maximizes usable battery voltage range down to 2.8 V. | Use Scenario: Compact USB-powered oscilloscope probes and logic analyzers drawing power directly from host USB port. IC Role / Device Role / Timing Role: Primary PMIC generating stable 1.2 V (FPGA core) and 2.5 V (I/O bank) from 5 V USB input, with PG signal synchronized to USB enumeration timing. Use Value: 2.0 MHz switching enables <1 mm² inductor area; open-drain PG provides direct interface to USB controller reset pin without level-shifting. |
| Industrial Edge Sensors | Wearable Health Monitors |
Use Scenario: Battery-operated vibration sensors deployed in factory predictive maintenance systems with 10-year deployment life. IC Role / Device Role / Timing Role: Power manager supplying 3.3 V to RF transceiver and 1.5 V to ultra-low-power microcontroller, with thermal protection for unventilated enclosures. Use Value: -40°C to +125°C rating ensures operation in hot machinery environments; 165°C thermal shutdown prevents damage during prolonged high-temperature exposure. | Use Scenario: Skin-contact ECG patches requiring continuous 24/7 operation on coin-cell batteries with sub-µA sleep current. IC Role / Device Role / Timing Role: Dual-output regulator enabling separate power domains for analog front-end (LDO) and digital processing (buck), with PG used to validate rail integrity before data acquisition. Use Value: Internal compensation and 1 µF LDO output cap minimize component count; sequenced shutdown avoids transient glitches during sleep entry. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-output regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TC1303C-ZP0EMF | Same dual-regulator architecture and pinout, but lacks sequenced startup/shutdown; PG monitors both outputs with identical 300 ms delay | Suitable where simultaneous rail enable is acceptable, e.g., simpler microcontroller systems without strict boot sequencing | Select TC1304-ZP0EMF when SoC or FPGA boot order mandates LDO-first sequencing; choose TC1303C-ZP0EMF for cost-sensitive designs without sequencing requirement |
| TPS65023RGTR | Triple-output PMIC (2 buck + 1 LDO), higher IQ (120 µA), no built-in sequencing logic, requires external GPIO control for ordering | Applicable in multi-rail systems needing >2 outputs, but adds firmware complexity and external components for sequencing | TC1304-ZP0EMF offers integrated sequencing in smaller footprint and lower IQ; TPS65023RGTR preferred only when third rail is required |
Compared with TC1303C-ZP0EMF and TPS65023RGTR, TC1304-ZP0EMF uniquely integrates hardware-based sequencing in a compact DFN package with lowest quiescent current, eliminating software dependency and external timing components while maintaining full pin compatibility with the TC1303 family.
Availability
TC1304-ZP0EMF is available at Aetrix Electronics and suitable for portable medical devices, USB-powered test equipment, industrial edge sensors, and wearable health monitors requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.
Supply support for TC1304-ZP0EMF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a leading provider of microcontrollers, analog components, and power management ICs, headquartered in Chandler, Arizona, with global manufacturing and support infrastructure.
The TC1303/TC1304 product line was designed specifically for space-constrained, battery-operated portable electronics requiring highly integrated, low-quiescent-current dual-rail power solutions with robust protection and sequencing capability.
FAQ
What is the function of the SHDN pin on the TC1304-ZP0EMF?
The SHDN pin on the TC1304-ZP0EMF is an active-high logic input that initiates hardware-controlled sequencing: it enables the LDO output (VOUT2) first, then the buck output (VOUT1) after a defined delay. When pulled low (<15% VIN), it disables both regulators in reverse order - LDO shuts down before buck - preventing backfeed and ensuring safe power cycling. This behavior is intrinsic to the TC1304-ZP0EMF and differs from TC1303 variants with separate SHDN1/SHDN2 pins.
Does the TC1304-ZP0EMF support adjustable output voltage on both regulators?
The TC1304-ZP0EMF supports adjustable output voltage only on the buck regulator (VOUT1), via external resistor divider connected to the VFB1/VOUT1 pin (0.8 V to 4.5 V range). The LDO output (VOUT2) is factory-trimmed to a fixed voltage - for TC1304-ZP0EMF, this is 3.3 V, as indicated by the "ZP" suffix per Microchip's part numbering scheme. No external adjustment is possible for VOUT2.
How does the power-good (PG) output behave on the TC1304-ZP0EMF?
The PG output on the TC1304-ZP0EMF is an open-drain signal that remains low until both VOUT1 and VOUT2 reach ≥94% of their target voltages, then asserts high after a fixed 300 ms delay. It monitors both regulators simultaneously - unlike TC1303A (buck-only) or TC1303B (LDO-only) - and is designed to drive standard processor reset inputs. The TC1304-ZP0EMF's PG pin requires an external pull-up resistor to the desired logic voltage.
What thermal performance can be expected from the TC1304-ZP0EMF in a 10-pin DFN package?
In a standard 4-layer PCB with internal ground plane and two thermal vias under the exposed pad, the TC1304-ZP0EMF achieves a junction-to-ambient thermal resistance (θJA) of 41°C/W. At full 500 mA buck + 300 mA LDO load with 5 V input and 3.3 V/1.8 V outputs, power dissipation remains below 0.5 W, keeping junction temperature rise under 21°C above ambient - well within the -40°C to +125°C operating range. Thermal shutdown activates at 165°C with 10°C hysteresis.
Can the TC1304-ZP0EMF operate with different input sources for VIN1 and VIN2?
No - the TC1304-ZP0EMF datasheet explicitly states that VIN1 and VIN2 must be supplied from the same input source (Note 8, DS21949C-page 7). Routing separate supplies risks violating internal biasing conditions, compromising regulation accuracy, and potentially damaging the device due to voltage differentials between AGND and PGND. For designs requiring independent inputs, discrete regulators or alternate PMICs with isolated inputs must be used instead of TC1304-ZP0EMF.
TC1304-ZP0EMF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 10-VFDFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Topology:
- Step-Down (Buck) Synchronous (1), Linear (LDO) (1)
- Number of Outputs:
- 2
- Frequency - Switching:
- 2MHz
- Voltage/Current - Output 1:
- Adj, 500mA
- Voltage/Current - Output 2:
- 1.8V, 300mA
- Voltage/Current - Output 3:
- -
- w/LED Driver:
- No
- w/Supervisor:
- No
- w/Sequencer:
- Yes
- Voltage - Supply:
- 2.7V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 10-DFN (3x3)
TC1304-ZP0EMF FAQ
1.How can I place an order for TC1304-ZP0EMF through Aetrix?
Please submit a Request for Quotation (RFQ) for TC1304-ZP0EMF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TC1304-ZP0EMF reliable?
The price and inventory of TC1304-ZP0EMF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TC1304-ZP0EMF is usually 5 days.
3.What payment methods are accepted for TC1304-ZP0EMF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TC1304-ZP0EMF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TC1304-ZP0EMF?
TC1304-ZP0EMF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TC1304-ZP0EMF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TC1304-ZP0EMF?
For technical support, including TC1304-ZP0EMF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TC1304-ZP0EMF requirements.
6.How does Aetrix verify that TC1304-ZP0EMF is sourced from the original manufacturer or authorized distributors?
All TC1304-ZP0EMF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TC1304-ZP0EMF meets industry standards.
7.What is the process for return or replacement of TC1304-ZP0EMF?
All TC1304-ZP0EMF units undergo pre-shipment inspection (PSI). If there is an issue with TC1304-ZP0EMF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TC1304-ZP0EMF part is unused and in its original packaging.
Return procedure for TC1304-ZP0EMF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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