Microchip Technology TC1304-ZP0EMFTR
- Part No.:
- TC1304-ZP0EMFTR
- Manufacturer:
- Microchip Technology
- Category:
- Voltage Regulators - Linear + Switching
- Package:
- 10-VFDFN Exposed Pad
- Datasheet:
-
TC1304-ZP0EMFTR.pdf
- Description:
- IC REG DL BUCK/LINEAR SYNC 10DFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
TC1304-ZP0EMFTR from Microchip Technology is a dual-output power management IC integrating a 500 mA synchronous buck regulator and a 300 mA low-dropout linear regulator (LDO), with sequenced startup/shutdown, 300 ms power-good delay, 65 µA typical quiescent current, and operation from -40°C to +125°C junction temperature. It delivers tightly regulated core and bias voltages for portable processors in USB-powered devices.
For engineers reviewing the TC1304-ZP0EMFTR datasheet, TC1304-ZP0EMFTR pinout, TC1304-ZP0EMFTR application, or TC1304-ZP0EMFTR equivalent, key selection criteria include output sequencing capability, dual-regulator efficiency trade-offs, PG monitoring of both outputs, thermal performance in 3×3 DFN, and compatibility with 1 µF LDO output capacitance.
Technical Context
The TC1304-ZP0EMFTR implements independent control logic for buck and LDO sections, with automatic PWM-to-PFM mode transition under light load to maintain ultra-low IQ. Its power-good generator monitors both VOUT1 and VOUT2 simultaneously and asserts after a fixed 300 ms delay upon regulation.
Sequencing is hardware-defined: during startup, the LDO enables first, followed by the buck regulator; during shutdown, the buck regulator disables before the LDO. The device uses internal compensation for both regulators and supports adjustable (0.8–4.5 V) or fixed VOUT1 options.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Buck Output Current | 500 mA maximum - supports processor core rails requiring moderate current at high efficiency |
| LDO Output Current | 300 mA maximum - supplies auxiliary I/O or memory bias with low noise and minimal external components |
| Quiescent Current | 65 µA typical - enables multi-day battery life in always-on portable systems |
| Power-Good Delay | 300 ms fixed - provides reliable reset timing for microcontrollers and FPGAs |
| Operating Temperature | -40°C to +125°C junction - qualified for industrial and automotive-adjacent embedded applications |
| Switching Frequency | 2.0 MHz fixed (heavy load) - allows compact 4.7 µH inductor and reduces EMI filtering burden |
| LDO Dropout Voltage | 137 mV typical @ 200 mA - minimizes input headroom requirement for 3.3 V or 2.5 V bias rails |
Pinout & Package
TC1304-ZP0EMFTR is housed in a 10-pin 3×3 mm DFN package with exposed thermal pad (EP), optimized for high-power-density portable designs. Pin numbering follows standard DFN orientation (pin 1 top-left, counterclockwise).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 - SHDN | Global shutdown input | Active-low logic control initiating sequenced enable/disable of both regulators |
| 2 - VIN2 | LDO input supply | Accepts 2.7–5.5 V input; must be tied closely to VIN1 for optimal PSRR |
| 3 - VOUT2 | LDO regulated output | Delivers 300 mA with ≤137 mV dropout; requires ≥1 µF ceramic capacitor to AGND |
| 4 - PG | Power-good open-drain output | Asserts low when both VOUT1 and VOUT2 are within ±6% of regulation; 300 ms delay built-in |
| 5 - AGND | Analog ground reference | Must connect to clean analog ground plane; separate from PGND for noise isolation |
| 6 - PGND | Power ground return | High-current return path for buck switch node; ties to AGND only at single point |
| 7 - LX | Buck switch node | Connects to external 4.7 µH inductor and catch diode; high dv/dt node requiring tight layout |
| 8 - VIN1 | Buck input supply | Accepts 2.7–5.5 V; shares input source with VIN2 per datasheet Note 8 |
| 9 - VFB1/VOUT1 | Buck feedback or output | Configurable: for fixed-output variants, connects directly to VOUT1; for adjustable, receives resistor divider |
| 10 - EP | Exposed thermal pad | Internally connected to AGND; must be soldered to PCB thermal plane for θJA = 41°C/W |
Key Features
| Feature | Design Value |
|---|---|
| Sequenced startup/shutdown | Hardware-enforced LDO-first startup and buck-first shutdown prevents backfeeding and ensures safe power domain sequencing |
| Both outputs internally compensated | Eliminates need for external compensation networks - reduces BOM count and layout sensitivity |
| 2.0 MHz fixed-frequency PWM | Enables use of small, low-profile inductors and simplifies EMI filter design vs. variable-frequency alternatives |
| Automatic PWM-to-PFM transition | Maintains >85% efficiency down to ~1 mA load without control-loop reconfiguration or external intervention |
| Open-drain PG with dual-output monitoring | Single reset signal confirms stability of both voltage rails - critical for SoC and FPGA power integrity validation |
| Overtemperature & short-circuit protection | Thermal shutdown at 165°C with 10°C hysteresis and cycle-by-cycle current limiting on both outputs |
Applications
| USB-Powered Portable Instrument | Industrial Handheld Terminal |
|---|---|
Use Scenario: Battery-operated handheld medical sensor with ARM Cortex-M4 MCU, display backlight, and analog front-end. IC Role / Device Role / Timing Role: Dual-rail power source: 1.2 V/500 mA for CPU core, 3.3 V/300 mA for peripherals and ADC; PG asserts after 300 ms to release MCU reset. Use Value: 65 µA IQ extends 2000 mAh Li-ion runtime beyond 7 days in sleep mode; sequenced startup prevents brown-out during boot. | Use Scenario: Ruggedized barcode scanner with integrated Wi-Fi module and flash memory, operating in warehouses from -20°C to +70°C ambient. IC Role / Device Role / Timing Role: Primary PMIC delivering 1.8 V/500 mA to application processor and 2.5 V/300 mA to RF transceiver; PG validates both rails before enabling radio firmware. Use Value: -40°C to +125°C junction rating ensures reliability across environmental extremes; 2.0 MHz switching avoids AM radio band interference. |
| Low-Power Edge AI Node | Programmable Logic Controller (PLC) I/O Module |
Use Scenario: Compact vision-based inference device using microcontroller with neural network accelerator, powered from USB-C PD port. IC Role / Device Role / Timing Role: Generates 0.9 V/500 mA for accelerator core and 3.3 V/300 mA for image sensor interface; sequenced shutdown prevents data corruption during power-down. Use Value: Adjustable VOUT1 supports future voltage scaling; 137 mV LDO dropout enables stable 3.3 V rail even as USB input sags to 3.6 V. | Use Scenario: DIN-rail mounted PLC expansion module with isolated RS-485, digital inputs, and real-time clock, powered from 24 VDC via internal DC-DC. IC Role / Device Role / Timing Role: Secondary regulator generating 1.2 V/500 mA for FPGA configuration and 2.5 V/300 mA for precision ADC reference; PG synchronizes with system watchdog timer. Use Value: Internal UVLO (2.55 V) prevents erratic behavior during brown-out; 41°C/W θJA in DFN enables convection-only cooling in sealed enclosure. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-output regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TC1303C-ZS0EMFTR | Same dual-regulator architecture and pinout, but lacks sequenced startup/shutdown; PG monitors both outputs identically | No hardware sequencing - requires external control logic for ordered enable/disable | Select when sequencing is managed externally or unnecessary; lower cost where timing control is software-defined |
| TPS65023RSBR | Triple-output (2 buck + 1 LDO), higher IQ (~120 µA), no built-in PG delay, different pinout and footprint | Supports more complex SoC power trees; requires redesign of layout and firmware timing | Choose for designs needing third rail or higher current; not drop-in - full schematic and layout revision required |
Compared with TC1303C-ZS0EMFTR and TPS65023RSBR, TC1304-ZP0EMFTR uniquely integrates hardware-enforced sequencing and dual-output PG in a space-constrained 3×3 DFN, making it optimal for compact, self-contained portable systems where deterministic power-up timing is critical.
Availability
TC1304-ZP0EMFTR is available at Aetrix Electronics and suitable for USB-powered portable instruments, industrial handheld terminals, low-power edge AI nodes, and programmable logic controller I/O modules requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for TC1304-ZP0EMFTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a U.S.-based semiconductor manufacturer specializing in microcontrollers, analog, interface, and power management solutions for industrial, automotive, and consumer markets.
The TC1303/TC1304 product line was designed to deliver highly integrated, low-quiescent-current dual-rail power solutions for space- and battery-constrained portable electronics, emphasizing simplicity, reliability, and minimal external component count.
FAQ
What is the function of the SHDN pin on the TC1304-ZP0EMFTR?
The SHDN pin on the TC1304-ZP0EMFTR is an active-low global shutdown input that initiates hardware-controlled sequencing: during startup, it enables the LDO first, then the buck regulator; during shutdown, it disables the buck regulator before the LDO. This prevents backfeeding and ensures safe power domain transitions without external timing circuitry. The TC1304-ZP0EMFTR requires SHDN to be pulled high (>45% of VIN) to activate both outputs.
Does the TC1304-ZP0EMFTR monitor both output voltages for its power-good signal?
Yes, the TC1304-ZP0EMFTR's PG pin is configured as an open-drain output that asserts low only when both VOUT1 (buck) and VOUT2 (LDO) are within ±6% of their nominal values - specifically, above 94% of regulation for each. This dual-monitoring behavior distinguishes it from TC1303A (buck-only) and TC1303B (LDO-only) variants, and the 300 ms delay is fixed and internal to the TC1304-ZP0EMFTR.
What is the minimum output capacitance required for the LDO section of the TC1304-ZP0EMFTR?
The LDO output (VOUT2) of the TC1304-ZP0EMFTR requires a minimum of 1 µF ceramic capacitor connected between VOUT2 and AGND for stable operation and proper transient response. The datasheet confirms this value is sufficient across all specified loads (up to 300 mA) and input conditions, eliminating need for larger or additional bulk capacitance in most portable applications.
Can the TC1304-ZP0EMFTR operate with separate input supplies on VIN1 and VIN2?
No - the TC1304-ZP0EMFTR datasheet explicitly states in Note 8 that VIN1 and VIN2 "are supplied by the same input source." Connecting independent supplies risks violating absolute maximum ratings and may cause unpredictable behavior due to internal biasing dependencies. Both pins must be tied together with short, low-inductance traces to a common 2.7–5.5 V source.
What thermal performance can be expected from the TC1304-ZP0EMFTR in its DFN package?
In its 10-lead 3×3 mm DFN package with exposed pad, the TC1304-ZP0EMFTR achieves a typical junction-to-ambient thermal resistance (θJA) of 41°C/W on a 4-layer PCB with internal ground plane and two thermal vias under the EP. This enables continuous 500 mA buck output at ambient temperatures up to +85°C without forced airflow, provided the EP is properly soldered to the PCB thermal plane.
TC1304-ZP0EMFTR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 10-VFDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Topology:
- Step-Down (Buck) Synchronous (1), Linear (LDO) (1)
- Number of Outputs:
- 2
- Frequency - Switching:
- 2MHz
- Voltage/Current - Output 1:
- Adj, 500mA
- Voltage/Current - Output 2:
- 1.8V, 300mA
- Voltage/Current - Output 3:
- -
- w/LED Driver:
- No
- w/Supervisor:
- No
- w/Sequencer:
- Yes
- Voltage - Supply:
- 2.7V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 10-DFN (3x3)
TC1304-ZP0EMFTR FAQ
1.How can I place an order for TC1304-ZP0EMFTR through Aetrix?
Please submit a Request for Quotation (RFQ) for TC1304-ZP0EMFTR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TC1304-ZP0EMFTR reliable?
The price and inventory of TC1304-ZP0EMFTR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TC1304-ZP0EMFTR is usually 5 days.
3.What payment methods are accepted for TC1304-ZP0EMFTR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TC1304-ZP0EMFTR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TC1304-ZP0EMFTR?
TC1304-ZP0EMFTR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TC1304-ZP0EMFTR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TC1304-ZP0EMFTR?
For technical support, including TC1304-ZP0EMFTR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TC1304-ZP0EMFTR requirements.
6.How does Aetrix verify that TC1304-ZP0EMFTR is sourced from the original manufacturer or authorized distributors?
All TC1304-ZP0EMFTR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TC1304-ZP0EMFTR meets industry standards.
7.What is the process for return or replacement of TC1304-ZP0EMFTR?
All TC1304-ZP0EMFTR units undergo pre-shipment inspection (PSI). If there is an issue with TC1304-ZP0EMFTR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TC1304-ZP0EMFTR part is unused and in its original packaging.
Return procedure for TC1304-ZP0EMFTR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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