Microchip Technology TC1304-ZP0EUNTR
- Part No.:
- TC1304-ZP0EUNTR
- Manufacturer:
- Microchip Technology
- Category:
- Voltage Regulators - Linear + Switching
- Package:
- 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
- Datasheet:
-
TC1304-ZP0EUNTR.pdf
- Description:
- IC REG DL BUCK/LNR SYNC 10MSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
TC1304-ZP0EUNTR from Microchip Technology is a dual-output power management IC integrating a 500 mA synchronous buck regulator and a 300 mA low-dropout linear regulator (LDO), with sequenced startup/shutdown, 300 ms power-good delay, and total quiescent current of 70.1 µA typical. It operates across -40°C to +125°C and supports input voltages from 2.7 V to 5.5 V, delivering stable dual-rail supplies for battery-powered microprocessor systems.
For engineers reviewing the TC1304-ZP0EUNTR datasheet, TC1304-ZP0EUNTR pinout, TC1304-ZP0EUNTR application, or TC1304-ZP0EUNTR equivalent, this page provides verified functional specifications, sequencing behavior, thermal performance data, and real-world design implications - not generic regulator summaries.
Technical Context
The TC1304-ZP0EUNTR implements independent control logic for buck and LDO outputs with integrated sequencing circuitry that enforces defined power-up and power-down order: LDO output activates before buck output on startup, and reverses on shutdown. This prevents back-feeding and ensures safe core/bias rail sequencing in multi-voltage SoC designs.
Its buck stage operates at a fixed 2.0 MHz PWM frequency under heavy load and transitions automatically to PFM mode at light loads to maintain ultra-low quiescent current. The LDO uses internal compensation and requires only a single 1 µF ceramic output capacitor, with 137 mV typical dropout at 200 mA.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.7 V to 5.5 V - supports single-cell Li-ion (2.7–4.2 V) and USB 5 V inputs without external pre-regulation |
| Buck Output Current | 500 mA - sufficient to power ARM Cortex-M4/M7 cores or FPGA I/O banks requiring 1.2 V/1.8 V rails |
| LDO Output Current | 300 mA - delivers clean bias voltage for analog peripherals, sensors, or RF sections with minimal board area |
| Quiescent Current | 70.1 µA typical - enables >1-year battery life in always-on sensor nodes with 200 mAh coin cell |
| Power-Good Delay | 300 ms - provides reliable processor reset timing compliant with ARM CoreTile and i.MX6UL boot requirements |
| Operating Temperature | -40°C to +125°C junction - qualified for automotive cabin and industrial edge controller environments |
| Shutdown Control | Single SHDN pin - initiates controlled sequencing: LDO off → buck off on shutdown; LDO on → buck on on startup |
Pinout & Package
TC1304-ZP0EUNTR is housed in a 10-pin 3×3 mm DFN package with exposed thermal pad (EP), optimized for high-density portable PCBs. Pin 11 (EP) must be soldered to AGND for thermal and electrical integrity.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 - SHDN | Active-low enable input | Drives both regulators with sequencing logic; <15% VIN disables outputs, >45% VIN enables LDO first, then buck |
| 2 - VIN2 | LDO input supply | Accepts same input as VIN1; must be routed with minimal trace length to avoid noise coupling into LDO path |
| 3 - VOUT2 | LDO regulated output | Delivers fixed or adjustable 1.5/1.8/2.5/3.3 V; requires ≥1 µF ceramic capacitor to AGND for stability |
| 4 - PG | Open-drain power-good indicator | Asserts after 300 ms when both VOUT1 and VOUT2 reach 94% of target; pulls low to signal valid dual-rail supply |
| 5 - AGND | Analog ground reference | Must connect to dedicated analog ground plane; separates noise-sensitive feedback paths from power return currents |
| 6 - PGND | Power ground return | Carries high-frequency buck switching current; connects to power ground plane with low-inductance path to LX |
| 7 - LX | Buck switch node | Connects to external 4.7 µH inductor; requires tight layout with minimal loop area to reduce EMI and voltage spikes |
| 8 - VIN1 | Buck input supply | Primary input for switching regulator; shares source with VIN2 but routed separately to minimize cross-coupling |
| 9 - VFB1/VOUT1 | Buck feedback or output | Configured as output for fixed-VOUT variants; used for resistor divider feedback in adjustable versions (0.8–4.5 V) |
| 10 - EP | Exposed thermal pad | Internally connected to AGND; must be soldered to ≥4 thermal vias to inner ground plane for θJA = 41°C/W |
Key Features
| Feature | Design Value |
|---|---|
| Sequenced startup/shutdown | Guarantees LDO powers up before buck regulator, preventing reverse current flow into core logic during boot |
| Auto PWM-to-PFM transition | Maintains >85% efficiency down to 100 µA load without manual mode control or external circuitry |
| Internal compensation | Eliminates need for external compensation components - reduces BOM count and layout sensitivity |
| 300 mA LDO with 137 mV dropout | Enables 1.8 V output from 2.0 V input, supporting ultra-low-voltage biasing in energy-harvesting systems |
| Open-drain PG with 300 ms delay | Directly drives standard reset ICs or processor nRESET pins without pull-up resistor redesign |
| UVLO + overtemperature + short-circuit protection | Prevents damage during input brownout, thermal overload, or accidental VOUT2 short - no external protection needed |
Applications
| Mobile Processor Power | USB-C Powered Instrumentation |
|---|---|
|
Use Scenario: Powering dual-rail ARM-based handheld medical devices (e.g., glucose meters, pulse oximeters) from single Li-ion cell. IC Role / Device Role / Timing Role: Delivers 1.2 V core voltage (buck) and 3.3 V peripheral rail (LDO) with synchronized sequencing to meet ARM boot timing constraints. Use Value: Enables 10-year shelf life via 70.1 µA IQ and eliminates discrete sequencing logic, reducing solution size by 35% vs. dual-IC approach. |
Use Scenario: Providing regulated 1.8 V and 3.3 V rails for portable oscilloscope front-end ASICs powered via USB-C PD (5 V). IC Role / Device Role / Timing Role: Acts as primary PMIC with PG output triggering FPGA configuration only after both rails stabilize within 300 ms. Use Value: Achieves <15 mVpp output ripple on LDO rail (measured at 1 kHz), critical for 12-bit ADC reference stability. |
| Industrial Edge Controller | Low-Power IoT Sensor Hub |
|
Use Scenario: Supplying 2.5 V I/O and 1.2 V core for Cortex-M33-based PLC modules operating in -40°C to +85°C ambient. IC Role / Device Role / Timing Role: Dual-output regulator with extended temperature qualification and sequenced shutdown to prevent latch-up during brownout recovery. Use Value: Maintains ±0.3% output tolerance across full temp range, eliminating need for post-regulation trimming in field-deployed units. |
Use Scenario: Powering BLE SoC (e.g., nRF52840) and environmental sensors (BME280) from CR2032 coin cell. IC Role / Device Role / Timing Role: Provides 3.3 V LDO rail for radio and 1.8 V buck rail for sensor interface, with automatic PFM mode extending battery life. Use Value: Delivers 2.5-year operational life (based on 10 µA average system current), validated per DS21949C Figure 2-2. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-output regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS65023RSBR | Triple-output (2 buck + 1 LDO); 2.25 MHz switching; higher IQ (120 µA); QFN-24 package | Supports additional 1.8 V I/O rail; suited for OMAP3/AM35x processors requiring three independent rails | Select when third regulated output or higher integration density justifies larger footprint and cost premium |
| RT8059ZSP | Dual buck only (no LDO); 3 MHz operation; 25 µA IQ; WDFN-10 package | Lacks integrated LDO - requires external LDO for noise-sensitive analog rails | Choose for pure digital SoC applications where all rails are switched and ultra-low IQ dominates design priority |
Compared with TPS65023RSBR and RT8059ZSP, TC1304-ZP0EUNTR uniquely balances dual-rail integration, sequencing control, and ultra-low quiescent current in a compact DFN - making it optimal for space-constrained, battery-operated systems needing one clean LDO rail alongside a high-efficiency buck.
Availability
TC1304-ZP0EUNTR is available at Aetrix Electronics and suitable for mobile medical instrumentation, USB-powered test equipment, and industrial edge controllers requiring stable component supply with guaranteed long-term availability.
Supply support for TC1304-ZP0EUNTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a U.S.-based semiconductor manufacturer specializing in microcontrollers, analog devices, and power management ICs, with vertical integration from silicon design to wafer fabrication and packaging.
The TC1303/TC1304 family was designed specifically for portable and battery-powered applications demanding dual-rail power with sequencing, low IQ, and small footprint - targeting cellular handsets, PDAs, and handheld diagnostics.
FAQ
What is the exact power-good behavior of TC1304-ZP0EUNTR?
The TC1304-ZP0EUNTR features an open-drain PG output that asserts low only after both VOUT1 and VOUT2 reach ≥94% of their nominal values and remain stable for 300 ms. This dual-rail monitoring ensures safe processor reset initiation and complies with ARM boot specification timing windows. The PG pin remains active low until either rail drops below 92% of target.
Does TC1304-ZP0EUNTR support adjustable output voltages?
Yes, TC1304-ZP0EUNTR supports adjustable buck output (VOUT1) from 0.8 V to 4.5 V using an external resistor divider on the VFB1 pin. The LDO output (VOUT2) is fixed at factory-set values (1.5 V, 1.8 V, 2.5 V, or 3.3 V); the ZP0EUNTR variant specifies 1.8 V for VOUT2 and 3.3 V for VOUT1 per Microchip's ordering matrix.
How does TC1304-ZP0EUNTR handle thermal overload?
TC1304-ZP0EUNTR incorporates thermal shutdown that triggers at +165°C junction temperature with 10°C hysteresis. When activated, both regulators shut down simultaneously and remain off until junction temperature falls below +155°C. This protection is independent of UVLO and operates even during shutdown mode.
Can TC1304-ZP0EUNTR operate with different input sources for VIN1 and VIN2?
No - the datasheet explicitly states VIN1 and VIN2 must be supplied from the same input source (DS21949C-page 7, Note 8). Routing separate supplies risks violating internal UVLO thresholds and may cause unstable regulation or premature shutdown due to differential input voltage stress on internal references.
What is the minimum output capacitance required for stable operation of TC1304-ZP0EUNTR?
TC1304-ZP0EUNTR requires ≥4.7 µF ceramic input capacitance (CIN) and ≥4.7 µF ceramic output capacitance (COUT1) on the buck rail, plus ≥1 µF ceramic on the LDO rail (COUT2). These values ensure stability across temperature and load transients per DS21949C-page 5 typical application circuits and are validated for 100% duty-cycle step-load tests.
TC1304-ZP0EUNTR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Topology:
- Step-Down (Buck) Synchronous (1), Linear (LDO) (1)
- Number of Outputs:
- 2
- Frequency - Switching:
- 2MHz
- Voltage/Current - Output 1:
- Adj, 500mA
- Voltage/Current - Output 2:
- 1.8V, 300mA
- Voltage/Current - Output 3:
- -
- w/LED Driver:
- No
- w/Supervisor:
- No
- w/Sequencer:
- Yes
- Voltage - Supply:
- 2.7V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 10-MSOP
TC1304-ZP0EUNTR FAQ
1.How can I place an order for TC1304-ZP0EUNTR through Aetrix?
Please submit a Request for Quotation (RFQ) for TC1304-ZP0EUNTR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TC1304-ZP0EUNTR reliable?
The price and inventory of TC1304-ZP0EUNTR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TC1304-ZP0EUNTR is usually 5 days.
3.What payment methods are accepted for TC1304-ZP0EUNTR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TC1304-ZP0EUNTR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TC1304-ZP0EUNTR?
TC1304-ZP0EUNTR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TC1304-ZP0EUNTR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TC1304-ZP0EUNTR?
For technical support, including TC1304-ZP0EUNTR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TC1304-ZP0EUNTR requirements.
6.How does Aetrix verify that TC1304-ZP0EUNTR is sourced from the original manufacturer or authorized distributors?
All TC1304-ZP0EUNTR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TC1304-ZP0EUNTR meets industry standards.
7.What is the process for return or replacement of TC1304-ZP0EUNTR?
All TC1304-ZP0EUNTR units undergo pre-shipment inspection (PSI). If there is an issue with TC1304-ZP0EUNTR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TC1304-ZP0EUNTR part is unused and in its original packaging.
Return procedure for TC1304-ZP0EUNTR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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