Texas Instruments TC247SPD-B0

Overview

TC247SPD-B0 from Texas Instruments is a 1/2-inch frame interline transfer monochrome CCD image sensor with 658(H) × 496(V) active pixels (340,000 total), integrated Peltier cooler and temperature sensor, charge multiplication gain up to 2000×, and 30 frames/s readout speed - designed for ultra-low-light scientific imaging, night vision, and high-sensitivity surveillance systems.

For engineers reviewing the TC247SPD-B0 datasheet, TC247SPD-B0 pinout, TC247SPD-B0 application, or TC247SPD-B0 equivalent, this page delivers verified technical context, validated pin functions, multimode readout timing constraints, CCM gain dependency on CMG voltage and temperature, and real-world low-noise performance metrics including 1.0 e⁻ noise-equivalent signal with typical charge multiplication.

Technical Context

The TC247SPD-B0 implements TI's proprietary Split-Gate Virtual-Phase CCD (SGVPCCD) architecture with dual-length serial register: first half handles standard charge transport from memory area, second half contains 400 dedicated charge multiplication stages using impact ionization under high-field gate pulses applied to CMG. Charge multiplication gain is electronically variable (1–2000×) via CMG high-level amplitude (5.5–6.5 V nominal, up to 22 V absolute max) and strongly temperature-dependent.

It supports progressive scan, pseudo-interlace, line summing, and pixel summing modes; integrates lateral overflow drain blooming protection without NIR response penalty; and uses correlated double sampling (CDS) compatible output with floating diffusion detection node and dual-stage source-follower buffer. Dark reference is provided by 20 shielded columns per line plus 4 isolated dark lines between sensing and storage areas.

Key Specifications

Pinout & Package

Dual-in-line ceramic package (SOCS091) with 24 leads, hermetically sealed glass window, integrated thermoelectric cooler (Peltier), and NTC thermistor. Package dimensions comply with standard DIP footprint; mounting holes spaced 1.78 mm center-to-center.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar monochrome CCD image sensor applications.

Compared with KAI-0340-CBA-JCEA and ICX285AQ, the TC247SPD-B0 uniquely delivers on-chip electron multiplication, integrated thermoelectric cooling, and sub-electron noise performance - making it irreplaceable for photon-limited applications requiring quantitative low-light imaging below 1 photon/pixel/frame.

Availability

TC247SPD-B0 is available at Aetrix Electronics and suitable for astronomy imaging systems, low-light surveillance cameras, scientific spectroscopy instruments, and biomedical microscopy platforms requiring stable component supply, long-term obsolescence management, and traceable sourcing.

Supply support for TC247SPD-B0 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and high-performance imaging technologies with over 50 years of CCD development expertise.

The TC247SPD-B0 belongs to TI's IMPACTRON™ family of ultra-low-noise, high-sensitivity CCDs engineered specifically for scientific, defense, and industrial applications demanding single-photon detection capability and thermal stability.

FAQ

What is the maximum allowable CMG voltage for reliable operation of the TC247SPD-B0?

The absolute maximum CMG input voltage is 22 V, but the recommended operating high-level range is 5.5–6.5 V. Exceeding 6.5 V increases risk of gate oxide stress and long-term reliability degradation, especially at elevated temperatures. The TC247SPD-B0 achieves optimal charge multiplication gain (up to 2000×) within the 5.5–6.5 V range while maintaining stable excess noise factor (≤1.4). Always reference the SOCS091 datasheet Figure 11 for temperature-compensated CMG voltage selection.

Does the TC247SPD-B0 require external CDS circuitry, and why?

Yes, the TC247SPD-B0 requires external correlated double sampling (CDS) circuitry to achieve its specified 1.0 e⁻ noise-equivalent signal performance. The on-chip floating diffusion and source-follower amplifier generate kTC reset noise that must be canceled; CDS removes this noise by sampling both reset and signal levels. Without CDS, the TC247SPD-B0 noise floor rises to 20 e⁻. The device's OUT pin timing (Figure 3) is explicitly designed for CDS compatibility, with defined clamp and sample windows referenced to SRG1 and RST edges.

How does the integrated Peltier cooler in the TC247SPD-B0 affect system thermal design?

The TC247SPD-B0's built-in Peltier cooler requires an external heat sink capable of dissipating ≥7 W at ΔT = 30°C (per Figure 12), with forced airflow ≥4.3 m/s. Failure to remove waste heat causes the CCD die temperature to rise above −20°C, increasing dark current exponentially (doubling every ~8°C) and degrading the 0.01 nA/cm² spec. Condensation must be avoided: the internal dew point must remain <−20°C, mandating strict environmental sealing and thermal interface material selection per TI's handling guidelines.

Can the TC247SPD-B0 operate without the Peltier cooler enabled?

Yes, the TC247SPD-B0 can operate with the Peltier cooler disabled, but only within the −20°C to +55°C free-air temperature range. At room temperature (25°C), dark current rises to ~0.8 nA/cm² (80× increase), dark signal increases to ~5 mV, and noise-equivalent signal degrades from 1.0 e⁻ to ~20 e⁻ - eliminating single-photon capability. The thermistor (THER pin) remains functional for ambient monitoring, but CCM gain stability and dynamic range (75 dB → 63 dB) are compromised without active cooling.

What is the purpose of the "dummy lines" (Line #−1 and Line #0) in TC247SPD-B0 progressive scan timing?

The first two lines (Line #−1 and Line #0) in TC247SPD-B0 progressive scan output contain no valid image data due to the dual-length serial register architecture: the second half (400-stage multiplier) introduces a 2-line latency before charge reaches the output node. These dummy lines must be discarded in firmware or FPGA logic. Their presence is inherent to the charge multiplication design and is documented in Figure 2-a timing diagram - skipping them ensures accurate pixel alignment and prevents vertical offset artifacts in final imagery.