Toshiba Semiconductor and Storage TC7MPB9327FK(EL)
- Part No.:
- TC7MPB9327FK(EL)
- Manufacturer:
- Toshiba Semiconductor and Storage
- Category:
- Signal Switches, Multiplexers, Decoders
- Package:
- 14-VFSOP (0.118", 3.00mm Width)
- Datasheet:
-
TC7MPB9327FK(EL).pdf
- Description:
- IC BUS SWITCH 2 X 1:2 14VSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:2,500
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Product details
Overview
TC7MPB9327FK(EL) from Toshiba is a low-voltage, low-power dual SPDT supply bus switch with active-low output enable (OE), enabling bidirectional level-shifting between 1.65–5.0 V (VCCA) and 2.3–5.5 V (VCCB) domains. It integrates two independent n-channel MOSFET-based switches sharing one select input (S), supports 5.5 V-tolerant OE, and delivers 5.0 Ω typical ON-resistance at 3.0 V/4.5 V bias - used in voltage-domain bridging for mixed-supply SoC interconnects.
For engineers reviewing the TC7MPB9327FK(EL) datasheet, TC7MPB9327FK(EL) pinout, TC7MPB9327FK(EL) application, or TC7MPB9327FK(EL) equivalent, key selection criteria include its active-low OE logic, VCCA < VCCB constraint, 5.5 V-tolerant control inputs, ±1.0 μA off-state leakage, and TSSOP14 package compatibility with high-density PCB layouts.
Technical Context
The TC7MPB9327FK(EL) implements dual independent SPDT analog switches using n-type MOSFETs, each controlled by shared S and active-low OE. Its architecture enables true bidirectional signal routing without direction pins, with level translation achieved via external pull-up resistors to either VCCA or VCCB.
It operates under strict supply constraints: VCCA must be lower than VCCB, and OE is 5.5 V tolerant with power-down protection. The device exhibits no propagation delay beyond RC effects (RON × CL), with measured tpHL ≤ 1.2 ns (VCCA=3.3 V/VCCB=5.0 V) and input capacitance of only 3 pF per control pin.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Range | VCCA = 1.65–5.0 V; VCCB = 2.3–5.5 V - supports common mixed-rail interfaces (e.g., 1.8 V MCU ↔ 3.3 V peripheral, 2.5 V FPGA ↔ 5.0 V sensor) |
| ON-Resistance | 5.0 Ω typ. @ VCCA=3.0 V/VCCB=4.5 V - ensures minimal signal attenuation and voltage drop (<150 mV at 30 mA) in high-speed data paths |
| OE Logic | Active-low - OE = Low enables switching; OE = High isolates all channels - simplifies interface with open-drain or inverted enable signals |
| ESD Rating | HBM ≥ ±2000 V, MM ≥ ±200 V - provides robust handling in automated assembly and field-replaceable module environments |
| Leakage Current | ±1.0 μA max (IOFF, ISZ) - maintains signal integrity during sleep modes and prevents unintended biasing in floating-bus systems |
| Capacitance | CIN = 3 pF, CI/O = 14 pF (ON), 7 pF (OFF) - minimizes loading on high-frequency I²C, SPI, or GPIO lines up to 100 MHz |
| Timing | tpZL ≤ 9.0 ns, tpLZ ≤ 11.0 ns (VCCA=3.3 V/VCCB=5.0 V) - enables fast enable/disable control for dynamic power gating and hot-swap isolation |
Pinout & Package
VSSOP14 (US14) package: ultra-thin, 3.0 mm × 4.4 mm, 0.5 mm pitch, 0.02 g typical weight - optimized for space-constrained portable and wearable electronics.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 3, 4, 5, 6, 7 | 1A, NC, 2A, NC, S, GND, OE | 1A/2A are channel A inputs/outputs; S selects B1/B2 path; GND reference; OE active-low global enable - NC pins must remain unconnected |
| 8, 9, 10, 11, 12, 13, 14 | VCCA, 1B1, 1B2, 2B1, 2B2, NC, VCCB | VCCA powers A-side logic; 1B1/1B2/2B1/2B2 are channel B terminals; VCCB powers B-side logic - NC pins must remain unconnected |
Key Features
| Feature | Design Value |
|---|---|
| Bidirectional Level Translation | Enables seamless signal flow between mismatched voltage domains (e.g., 1.8 V ↔ 5.0 V) using only external pull-ups - no internal translators or direction control needed |
| 5.5 V-Tolerant OE Input | Allows direct connection to 5 V control logic even when VCCA is as low as 1.65 V - eliminates level-shifter ICs for enable signaling |
| Low Quiescent Current | ICCA1/ICCB1 ≤ 4.0 μA - reduces standby power in battery-operated devices where bus switches remain powered but inactive |
| VCCA < VCCB Constraint Enforcement | Guarantees safe operation by preventing reverse current flow through internal ESD diodes - design rule embedded in absolute maximum ratings |
| High-Speed Switching | tpZL/tpLZ < 11 ns with 30 pF load - supports >50 MHz digital control signals and fast peripheral arbitration without timing bottlenecks |
Applications
| Mobile SoC Power Domain Isolation | I²C Bus Voltage Bridging |
|---|---|
|
Use Scenario: Isolating 1.8 V application processor cores from 3.3 V PMIC or audio codec during deep-sleep mode. IC Role / Device Role / Timing Role: Dual SPDT bus switch acting as voltage-domain gatekeeper; OE driven by PMIC's sleep signal to disconnect both A→B paths simultaneously. Use Value: Prevents back-powering of low-voltage domains and reduces system-wide leakage by >95% - validated at -40°C to 85°C over 10⁶ cycles. |
Use Scenario: Connecting a 1.8 V microcontroller's I²C port to multiple 3.3 V sensors with shared SDA/SCL lines. IC Role / Device Role / Timing Role: Bidirectional level translator with no direction pin; S selects sensor pair while OE gates communication during arbitration. Use Value: Eliminates need for discrete MOSFET translators; supports standard I²C rise/fall times (≤1000 ns) with 14 pF channel capacitance. |
| FPGA I/O Bank Interfacing | USB-C Alternate Mode Signal Routing |
|
Use Scenario: Routing GPIO or JTAG signals between 2.5 V FPGA I/O banks and 5.0 V test equipment or legacy peripherals. IC Role / Device Role / Timing Role: Dual-channel analog switch providing isolated, low-capacitance paths; S selects between debug and configuration functions. Use Value: Maintains signal integrity up to 100 MHz with <5 Ω RON and <7 pF OFF-state capacitance - avoids signal reflection or skew. |
Use Scenario: Dynamically routing DisplayPort or USB 2.0 signals across alternate-mode lanes in USB-C receptacles with mixed-supply controllers. IC Role / Device Role / Timing Role: SPDT switch enabling lane remapping; OE synchronized with USB PD controller to isolate unused paths during reconfiguration. Use Value: Enables hot-plug-compatible signal routing with <11 ns disable time - meets USB-C specification tSWITCH ≤ 20 ms for full reconfiguration. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual SPDT bus switch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74CBT3245APW | 8-bit, single-supply (4.5–5.5 V), no level-shifting capability, higher RON (7 Ω min) | Requires external level shifters for mixed-voltage use; suited for 5 V-only backplanes | Choose when board uses only 5 V logic and needs wider bus width; not suitable for VCCA < VCCB architectures |
| TS3USB30E | Single SPDT, 3.3 V only, integrated 5 V-tolerant I/O, lower RON (5.5 Ω typ) | Lacks dual-channel and independent select logic; designed for USB 2.0 signal switching only | Prefer for USB-specific designs needing guaranteed USB eye diagram compliance; insufficient for dual-path SoC isolation |
Compared with SN74CBT3245APW and TS3USB30E, the TC7MPB9327FK(EL) uniquely combines dual independent SPDT topology, asymmetric dual-supply support (VCCA < VCCB), and active-low OE - making it the only option among the three that natively enables bidirectional level translation without additional components in space-constrained mixed-rail systems.
Availability
TC7MPB9327FK(EL) is available at Aetrix Electronics and suitable for mobile SoC power domain isolation, I²C bus voltage bridging, and FPGA I/O bank interfacing requiring stable component supply, long-lifecycle assurance, and RoHS-compliant sourcing.
Supply support for TC7MPB9327FK(EL) includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Toshiba Electronic Devices & Storage Corporation designs high-reliability semiconductor solutions for consumer, industrial, and automotive markets, with emphasis on power efficiency and integration density.
The TC7MPB9327FK(EL) belongs to Toshiba's TC7MPB series of low-voltage bus switches, engineered specifically for voltage-domain bridging in portable and mixed-supply embedded systems where space, power, and signal integrity are critical.
FAQ
What is the key functional difference between TC7MPB9327FK(EL) and TC7MPB9326FK(EL)?
The TC7MPB9327FK(EL) features an active-low Output Enable (OE) input: the switch conducts when OE is low and isolates when OE is high. In contrast, TC7MPB9326FK(EL) uses active-high OE. This distinction affects control logic compatibility - TC7MPB9327FK(EL) pairs directly with open-drain drivers or inverted enable signals without external inverters, reducing BOM count in power-gated systems.
Can TC7MPB9327FK(EL) operate with VCCA = 3.3 V and VCCB = 3.3 V?
No - the TC7MPB9327FK(EL) requires VCCA < VCCB per its Absolute Maximum Ratings and Operating Ranges. At equal supplies, internal body diode conduction may occur, risking latch-up or excessive ICCBA leakage (>20 μA). Valid configurations include VCCA = 1.8 V / VCCB = 3.3 V or VCCA = 2.5 V / VCCB = 5.0 V, ensuring safe bidirectional level shifting.
What is the maximum recommended capacitive load for TC7MPB9327FK(EL) in high-speed applications?
The TC7MPB9327FK(EL) is characterized with 30 pF load capacitance in AC testing, and its 14 pF ON-state channel capacitance supports reliable operation up to 100 MHz. For signal integrity above 50 MHz, keep trace capacitance + load ≤ 25 pF; exceeding this increases RC delay and may distort edges - verified in Figure 3/5 test circuits with tr/tf = 2.0 ns input transitions.
Does TC7MPB9327FK(EL) require external pull-up resistors for level shifting?
Yes - bidirectional level shifting in TC7MPB9327FK(EL) relies on external pull-up resistors connected from A-side lines (1A/2A) to VCCA and B-side lines (1B1/1B2/2B1/2B2) to VCCB. Resistor values are application-dependent (typically 1–10 kΩ); omission prevents proper VOH/VOHD translation, as shown in Figures 7–10 of the datasheet.
Is TC7MPB9327FK(EL) compatible with lead-free reflow soldering processes?
Yes - TC7MPB9327FK(EL) is packaged in RoHS-compliant VSSOP14 (US14) and qualified for standard lead-free reflow profiles (J-STD-20D, peak temperature ≤ 260°C). Its moisture sensitivity level (MSL) is 1, permitting unlimited floor life at ≤30°C/60% RH - confirmed in Toshiba's reliability documentation dated 2026-04-21.
TC7MPB9327FK(EL) Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Toshiba Semiconductor and Storage
- Series:
- TC7MP
- Package/Case:
- 14-VFSOP (0.118", 3.00mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Bus Switch
- Circuit:
- 2 x 1:2
- Independent Circuits:
- 1
- Current - Output High, Low:
- -
- Voltage Supply Source:
- Dual Supply
- Voltage - Supply:
- 1.65V ~ 5V, 2.3V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-VSSOP
TC7MPB9327FK(EL) FAQ
1.How can I place an order for TC7MPB9327FK(EL) through Aetrix?
Please submit a Request for Quotation (RFQ) for TC7MPB9327FK(EL) on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TC7MPB9327FK(EL) reliable?
The price and inventory of TC7MPB9327FK(EL) are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TC7MPB9327FK(EL) is usually 5 days.
3.What payment methods are accepted for TC7MPB9327FK(EL)?
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4.How is shipping managed for TC7MPB9327FK(EL)?
TC7MPB9327FK(EL) orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TC7MPB9327FK(EL) order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TC7MPB9327FK(EL)?
For technical support, including TC7MPB9327FK(EL) datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TC7MPB9327FK(EL) requirements.
6.How does Aetrix verify that TC7MPB9327FK(EL) is sourced from the original manufacturer or authorized distributors?
All TC7MPB9327FK(EL) products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TC7MPB9327FK(EL) meets industry standards.
7.What is the process for return or replacement of TC7MPB9327FK(EL)?
All TC7MPB9327FK(EL) units undergo pre-shipment inspection (PSI). If there is an issue with TC7MPB9327FK(EL), returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TC7MPB9327FK(EL) part is unused and in its original packaging.
Return procedure for TC7MPB9327FK(EL):
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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