Toshiba Semiconductor and Storage TC7QPB9307FK(EL)
- Part No.:
- TC7QPB9307FK(EL)
- Manufacturer:
- Toshiba Semiconductor and Storage
- Category:
- Signal Switches, Multiplexers, Decoders
- Package:
- 14-VFSOP (0.118", 3.00mm Width)
- Datasheet:
-
TC7QPB9307FK(EL).pdf
- Description:
- IC BUS SWITCH 4 X 1:1 14VSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
TC7QPB9307FK from Toshiba Electronic Devices & Storage Corporation is an active-low 4-bit dual-supply bus switch enabling bidirectional level translation between 1.65–5.0 V (VCCA) and 2.3–5.5 V (VCCB) domains. It uses n-channel MOSFET channels, delivers ≤8.0 Ω ON-resistance at 3.0 V/4.5 V, supports 5.5 V-tolerant OE input with power-down protection, and operates across –40°C to +85°C for mixed-voltage interconnect in FPGA-to-ASIC or microcontroller-to-peripheral interfaces.
For engineers reviewing the TC7QPB9307FK datasheet, TC7QPB9307FK pinout, TC7QPB9307FK application, or TC7QPB9307FK equivalent, this page provides verified voltage domain compatibility, confirmed OE polarity, validated ON-resistance and leakage specs, package-dimension-matched pin assignment, and two functionally comparable alternatives for voltage-level bridging designs requiring active-low enable control.
Technical Context
The TC7QPB9307FK implements four independent n-MOSFET transmission gates controlled by a single active-low Output Enable (OE) signal. Its dual-supply architecture allows VCCA and VCCB to operate at different voltages without sequencing constraints, provided VCCA < VCCB per datasheet Note 1.
Level shifting relies on external pull-up resistors tied to either VCCA or VCCB - no internal translators or direction pins are used. The device exhibits ≤11.0 ns output disable time (tPLZ) at 3.3 V/5.0 V and ≤7 pF OFF-capacitance, minimizing signal integrity impact in high-speed digital interconnects.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Range (VCCA) | 1.65 V to 5.0 V - enables interface with 1.8 V, 2.5 V, and 3.3 V logic domains |
| Supply Range (VCCB) | 2.3 V to 5.5 V - supports 2.5 V, 3.3 V, and 5.0 V buses while maintaining VCCA < VCCB constraint |
| ON-resistance (RON) | 8.0 Ω max @ VCCA = 3.0 V, VCCB = 4.5 V - ensures low insertion loss and minimal voltage drop under 30 mA load |
| OE Polarity | Active-Low - OE = Low enables all 4 channels; OE = High isolates A/B ports, critical for bus arbitration |
| Input Tolerance | 5.5 V tolerant OE pin - allows direct connection to 5 V control logic without level-shifting circuitry |
| Leakage Current | ±1.0 µA max (IOFF) - guarantees high isolation between powered and unpowered domains during sleep states |
| Operating Temperature | –40°C to +85°C - qualified for industrial-grade embedded systems with ambient thermal cycling |
Pinout & Package
VSSOP14 (US14) package: 3.0 mm × 4.4 mm body, 0.65 mm pitch, 0.9 mm max height, 0.02 g typical weight. Exposed pad not present. RoHS-compliant, lead-free finish.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (OE) | Output Enable (active-low) | Global control: Low enables all 4 switches; High disconnects A/B ports with <±1.0 µA leakage |
| 2 (A1) | Port A data line 1 | Bidirectional I/O: connects to lower-voltage domain (VCCA); requires external pull-up for level translation |
| 3 (B1) | Port B data line 1 | Bidirectional I/O: connects to higher-voltage domain (VCCB); referenced to VCCB for output high level |
| 4 (A2) | Port A data line 2 | Independent channel - electrically isolated from other A/B pairs; same VCCA/VCCB biasing rules apply |
| 5 (B2) | Port B data line 2 | Independent channel - supports simultaneous 4-bit translation without crosstalk or timing skew |
| 6 (A3) | Port A data line 3 | Same electrical characteristics as A1/A2; shares OE but not supply rails - VCCA must be common across all A pins |
| 7 (B3) | Port B data line 3 | Same electrical characteristics as B1/B2; VCCB must be common across all B pins |
| 8 (GND) | Ground reference | Common return for both supplies - required for proper ESD protection and RON stability |
| 9 (A4) | Port A data line 4 | Final channel of 4-bit group; no internal termination - external pull-ups define logic high level per domain |
| 10 (B4) | Port B data line 4 | Final channel; supports full 4-bit parallel translation (e.g., address/data bus segments) |
| 11 (VCCA) | Lower-voltage supply | Must be ≤ VCCB; powers internal logic and defines A-side logic thresholds (VIH/VIL) |
| 12 (VCCB) | Higher-voltage supply | Must be ≥ VCCA; sets B-side output swing and clamp diode limits (max 5.5 V) |
| 13 (NC) | No Connect | Internally unused - must remain floating or grounded per PCB layout best practice; no routing required |
| 14 (NC) | No Connect | Internally unused - identical handling as Pin 13; no electrical function or thermal role |
Key Features
| Feature | Design Value |
|---|---|
| Asymmetric dual-supply operation | VCCA (1.65–5.0 V) and VCCB (2.3–5.5 V) support mixed-voltage SoC interfacing without level-shifter ICs |
| Active-low global enable | Single OE pin controls all 4 channels with guaranteed <11 ns disable time - simplifies timing-critical bus isolation |
| 5.5 V-tolerant OE input | Accepts 5 V control signals directly while powered from 1.8 V VCCA - eliminates external buffer for legacy MCU GPIO |
| Low ON-resistance | 8.0 Ω max ensures <240 mV drop at 30 mA - preserves signal integrity for 3.3 V LVTTL and 2.5 V HSTL buses |
| ESD-protected inputs | HBM ±2 kV rating on all pins - meets IEC 61000-4-2 Level 2 for board-level robustness in manufacturing and field use |
Applications
| Industrial PLC I/O Expansion | FPGA-to-Microcontroller Interface |
|---|---|
Use Scenario: Connecting 3.3 V FPGA I/O banks to 5.0 V industrial sensor modules via shared address/data bus. IC Role / Device Role / Timing Role: Bidirectional level translator and bus isolator, enabling safe communication without voltage conflict or latch-up risk. Use Value: Eliminates need for discrete MOSFET translators; 8.0 Ω RON maintains signal rise/fall times under 30 pF load for 25 MHz bus operation. |
Use Scenario: Interfacing 1.8 V ARM Cortex-M4 GPIO to 2.5 V ADC SPI lines in portable medical instrumentation. IC Role / Device Role / Timing Role: Voltage-domain bridge with active-low OE synchronized to SPI chip-select assertion for precise timing control. Use Value: 5.5 V-tolerant OE accepts 2.5 V CS signal directly; ≤11 ns disable time prevents bus contention during mode transitions. |
| Automotive Infotainment Debug Port | Legacy Embedded System Upgrade |
Use Scenario: Adapting 5.0 V CAN transceiver debug interface to 3.3 V diagnostic controller in Tier-1 infotainment head unit. IC Role / Device Role / Timing Role: Isolation switch enabling hot-plug-safe debug access while main system remains powered. Use Value: Power-down protection on OE prevents back-powering when VCCA is off; ±1.0 µA IOFF ensures zero current drain during sleep. |
Use Scenario: Retrofitting 2.5 V microcontroller subsystem into existing 5.0 V industrial controller chassis with shared memory bus. IC Role / Device Role / Timing Role: 4-bit parallel translator replacing obsolete discrete solutions, preserving PCB footprint and signal routing. Use Value: VSSOP14 package matches legacy US14 footprints; identical pinout to TC7QPB9306FK except OE polarity - simplifies design reuse. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-supply bus switch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TC7QPB9306FK | Identical pinout and electrical specs, but OE is active-High instead of active-Low | Requires inverted enable logic; unsuitable where control signal polarity is fixed and non-invertible | Select TC7QPB9306FK only if system GPIO drives OE high to enable - verify timing margins for tPZL/tPLZ asymmetry |
| SN74AVC4T245RTER | TI part with auto-direction sensing, 3.6 V max VCC, no 5.5 V OE tolerance, different pinout (16-pin VQFN) | Cannot replace TC7QPB9307FK in 5 V-tolerant or VCCA > 3.6 V designs; requires PCB redesign | Choose SN74AVC4T245RTER only for new 1.8/3.3 V-only systems needing directionless operation - not a drop-in replacement |
Compared with TC7QPB9306FK and SN74AVC4T245RTER, the TC7QPB9307FK uniquely combines 5.5 V-tolerant active-Low OE, asymmetric 1.65–5.0 V / 2.3–5.5 V supply support, and VSSOP14 pin compatibility - making it optimal for industrial upgrades requiring polarity-matched, 5 V-safe bus isolation without layout changes.
Availability
TC7QPB9307FK is available at Aetrix Electronics and suitable for industrial PLC I/O expansion, FPGA-to-microcontroller interfacing, automotive infotainment debug ports, and legacy embedded system upgrades requiring stable component supply and long-term obsolescence management.
Supply support for TC7QPB9307FK includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Toshiba Electronic Devices & Storage Corporation designs and manufactures discrete semiconductors, power devices, and logic ICs for industrial, automotive, and consumer applications with emphasis on reliability and energy efficiency.
The TC7QPB9307FK belongs to Toshiba's TC7QP series of dual-supply bus switches, engineered specifically for voltage-level bridging in mixed-supply embedded systems where supply sequencing, power-down safety, and compact packaging are critical.
FAQ
What is the correct supply voltage relationship for TC7QPB9307FK?
The TC7QPB9307FK requires VCCA to be strictly less than VCCB per datasheet Note 1. Valid combinations include 1.8 V/3.3 V, 2.5 V/5.0 V, and 3.3 V/5.0 V. Violating this constraint risks latch-up or permanent damage. The TC7QPB9307FK does not support VCCA ≥ VCCB operation under any condition.
How does the active-Low OE pin affect timing in TC7QPB9307FK?
The TC7QPB9307FK OE pin asserts channel conduction when driven low, with 9.0–19.0 ns enable/disable delays depending on supply pair (e.g., 9.0 ns tPZL at 3.3 V/5.0 V). This active-Low behavior aligns with standard chip-select protocols, and the TC7QPB9307FK's 5.5 V tolerance allows direct connection to 5 V controllers without level shifters.
Can TC7QPB9307FK translate signals from 5.0 V down to 1.8 V?
Yes - the TC7QPB9307FK supports bidirectional level translation across its full rated ranges: VCCA = 1.65–5.0 V and VCCB = 2.3–5.5 V. For 5.0 V → 1.8 V translation, tie Bn pins to 5.0 V domain and An pins to 1.8 V domain with appropriate pull-ups; the TC7QPB9307FK's n-MOSFET structure inherently handles down-translation safely.
What is the maximum capacitive load the TC7QPB9307FK can drive reliably?
The TC7QPB9307FK is characterized with 30 pF load capacitance in AC testing and exhibits ≤14 pF typical ON-capacitance (CI/O). It reliably drives up to 30 pF loads at ≤25 MHz with <1.2 ns propagation delay (tPLH/tPHL) when VCCA = 3.3 V and VCCB = 5.0 V. Exceeding 30 pF increases RC delay and may degrade edge rates in the TC7QPB9307FK's signal path.
Does TC7QPB9307FK require external pull-up resistors for level shifting?
Yes - the TC7QPB9307FK requires external pull-up resistors on An and/or Bn lines to establish valid logic-high levels in each domain. Pull-up to VCCA sets A-side high level; pull-up to VCCB sets B-side high level. The TC7QPB9307FK contains no internal pull-ups, and omitting them results in undefined outputs during switching.
TC7QPB9307FK(EL) Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Toshiba Semiconductor and Storage
- Series:
- TC7QP
- Package/Case:
- 14-VFSOP (0.118", 3.00mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Bus Switch
- Circuit:
- 4 x 1:1
- Independent Circuits:
- 1
- Current - Output High, Low:
- -
- Voltage Supply Source:
- Dual Supply
- Voltage - Supply:
- 1.65V ~ 5V, 2.3V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-VSSOP
TC7QPB9307FK(EL) FAQ
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7.What is the process for return or replacement of TC7QPB9307FK(EL)?
All TC7QPB9307FK(EL) units undergo pre-shipment inspection (PSI). If there is an issue with TC7QPB9307FK(EL), returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TC7QPB9307FK(EL) part is unused and in its original packaging.
Return procedure for TC7QPB9307FK(EL):
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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