Texas Instruments TCA9801DGKR
- Part No.:
- TCA9801DGKR
- Manufacturer:
- Texas Instruments
- Category:
- Translators, Level Shifters
- Package:
- Datasheet:
-
TCA9801DGKR.pdf
- Description:
- IC TRANSLTR BIDIRECTIONAL 8VSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:4,062
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
TCA9801DGKR from Texas Instruments is a dual-channel bidirectional I²C/SMBus level-translating buffer with integrated B-side current source (1.1 mA typical), supporting 0.8 V–3.6 V on A-side and 1.65 V–3.6 V on B-side, ultra-low quiescent current (23 µA total at 1.8 V), and true buffering without static voltage offset - deployed in server backplanes to isolate 0.9 V processor I²C buses from 3.3 V sensor subsystems.
For engineers reviewing the TCA9801DGKR datasheet, TCA9801DGKR pinout, TCA9801DGKR application, or TCA9801DGKR equivalent, key selection criteria include B-side current source strength (1.1 mA), bus capacitance limit (400 pF), propagation delay (75–260 ns), no external B-side pull-ups required, and power sequencing independence (VCCA ≷ VCCB).
Technical Context
The TCA9801DGKR implements true bidirectional buffering-not pass-FET translation-using an internal current source on the B-side to detect bus contention and eliminate static voltage offsets. This enables sub-0.26 V VOL on both sides and eliminates fixed-VIL threshold conflicts in mixed-voltage I²C systems.
It supports clock stretching and multi-master arbitration while enforcing strict B-side input low detection via IILC (500 µA) and RILC (150 Ω), requiring no external pull-ups on SDAB/SCLB and prohibiting any external current injection into those pins to maintain reliable low-level recognition.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| A-side supply range | 0.8 V to 3.6 V - enables direct interface with sub-1 V processors and 1.8/3.3 V logic without level-shifter cascading |
| B-side supply range | 1.65 V to 3.6 V - compatible with 1.8 V, 2.5 V, and 3.3 V I²C slave domains; UVLO thresholds prevent false activation below 1.3 V |
| B-side current source | 1.1 mA typical (±25%) - replaces external pull-up resistors on SDAB/SCLB, improves rise time, and enables 400 kHz operation at ≤400 pF load |
| Propagation delay | 75–260 ns (A↔B) - ensures timing compliance in high-speed SMBus/PMBus systems with tight setup/hold margins |
| Total quiescent current | 23 µA at 1.8 V/1.8 V - reduces standby power in battery-backed or thermally constrained applications such as embedded controllers |
| Bus capacitance limit | 400 pF on B-side only - defines maximum trace + slave pin capacitance before signal integrity degrades; A-side has no cap limit |
| Enable input logic | Active-high referenced to VCCA with 150–450 kΩ internal pull-up - allows clean isolation of misbehaving slaves during power-up without external components |
Pinout & Package
VSSOP-8 (DGK) package, 3.00 mm × 3.00 mm body size, 0.65 mm pitch, exposed pad not present.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 - VCCA | A-side supply input | Reference for SCLA/SDAA I/O and EN logic; powers A-side circuitry; UVLO triggers at 0.3–0.55 V |
| 2 - SCLA | A-side serial clock I/O | Connects to A-side master/slave clock line; requires external pull-up to VCCA even if unused |
| 3 - SDAA | A-side serial data I/O | Connects to A-side master/slave data line; requires external pull-up to VCCA even if unused |
| 4 - GND | Ground reference | Common return for all supplies and I/O; must be low-impedance connection to avoid noise coupling |
| 5 - EN | Active-high enable input | Controls repeater function; high = bidirectional pass-through; low = A-side pins high-Z, B-side current source remains active if VCCB powered |
| 6 - SDAB | B-side serial data I/O | Connects to B-side slaves; no external pull-up allowed - internal 1.1 mA current source provides pull-up; floating if unused |
| 7 - SCLB | B-side serial clock I/O | Connects to B-side slaves; no external pull-up allowed - internal 1.1 mA current source provides pull-up; floating if unused |
| 8 - VCCB | B-side and device core supply | Powers B-side I/O and internal current source; UVLO disables current source below 1.2–1.6 V; independent of VCCA sequencing |
Key Features
| Feature | Design Value |
|---|---|
| Integrated B-side current source | 1.1 mA typical eliminates need for external pull-up resistors on SDAB/SCLB, reducing BOM count and PCB area |
| No static voltage offset | VOL ≤ 0.26 V on both sides prevents communication failure when interfacing with I²C devices having low VIL thresholds (e.g., < 0.3×VCC) |
| Power sequencing independence | VCCA and VCCB may power up/down in any order - no dependency or lock-up risk, simplifying system power management |
| Powered-off high-impedance A-side | SCLA/SDAA enter high-Z state when VCCA or VCCB falls below UVLO - safe to retain I²C wiring during power loss or reset |
| Back-power protection | All I²C pins include protection circuitry blocking current flow from bus lines into VCCA/VCCB - prevents unintended power injection |
Applications
| Server Backplane I²C Isolation | Rack-Mount Industrial Controller |
|---|---|
Use Scenario: Isolating a 0.9 V ARM-based baseboard management controller (BMC) I²C bus from 3.3 V hot-swap power modules and temperature sensors across a 15 cm backplane trace. IC Role / Device Role / Timing Role: Bidirectional level-translating repeater enabling clock/data translation between mismatched voltage domains while preserving SMBus timing and arbitration behavior. Use Value: Eliminates external B-side pull-ups and avoids VOL-induced NACKs due to VIL threshold violations, ensuring reliable PMBus communication at 100 kHz under thermal stress. |
Use Scenario: Interfacing a 1.8 V FPGA I²C master to legacy 2.5 V EEPROMs and 3.3 V ADCs in a DIN-rail mounted PLC with wide ambient temperature range (−40 °C to +85 °C). IC Role / Device Role / Timing Role: Dual-channel buffer providing voltage domain separation and bus capacitance management across mixed-voltage peripheral clusters. Use Value: Enables single-chip solution for multi-supply I²C expansion without redesigning pull-up networks or adding discrete FET translators. |
| Low-Power Edge Sensor Hub | PC Embedded Controller Interface |
Use Scenario: Connecting ultra-low-power 0.8 V IoT microcontroller I²C to 1.8 V environmental sensors (humidity, pressure) in battery-operated edge node with 10-year target lifetime. IC Role / Device Role / Timing Role: Level-shifting repeater minimizing standby current draw while maintaining full I²C protocol compliance including clock stretching. Use Value: Achieves 23 µA total quiescent current at 1.8 V, extending battery life versus discrete resistor+MOSFET solutions consuming >100 µA. |
Use Scenario: Bridging Intel PCH SMBus (1.05 V) to 3.3 V TPM, fan controllers, and thermal diodes in thin-client desktop motherboards with space-constrained layout. IC Role / Device Role / Timing Role: Voltage-domain translator enabling backward compatibility with legacy peripherals without altering existing 3.3 V bus topology. Use Value: Removes need for dual-rail power delivery to I²C peripherals and avoids timing margin loss from RC delays introduced by discrete level shifters. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar I²C level-translating repeater applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TCA9802DGKR | Higher B-side current source (2.2 mA vs. 1.1 mA); same pinout and voltage ranges | Better suited for heavier bus loads (>400 pF) or higher-frequency 400 kHz SMBus with marginal rise times | Select when driving >20 I²C slaves or long traces exceeding 15 cm; otherwise TCA9801DGKR offers lower power and sufficient drive |
| TCA9800DGKR | Lower B-side current source (0.54 mA vs. 1.1 mA); identical functional architecture and pinout | Optimized for ultra-low-capacitance buses (<100 pF) and minimal power draw where rise time margin is ample | Prefer for space-constrained wearables with <5 slaves and <5 cm trace length; TCA9801DGKR provides better noise immunity and robustness |
Compared with TCA9800DGKR and TCA9802DGKR, the TCA9801DGKR delivers optimal balance of drive strength (1.1 mA), power efficiency (23 µA), and bus capacitance support (400 pF), making it the default choice for mainstream server, industrial, and embedded I²C isolation where design margin and component count are critical.
Availability
TCA9801DGKR is available at Aetrix Electronics and suitable for server backplanes, industrial controllers, and low-power sensor hubs requiring stable component supply, long-term lifecycle assurance, and guaranteed traceable sourcing.
Supply support for TCA9801DGKR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor company specializing in analog, embedded processing, and connectivity technologies, with over 90 years of innovation in power management and interface solutions.
The TCA9801DGKR belongs to TI's I²C/SMBus level-translating repeater product line, designed specifically to solve voltage-domain interoperability and bus loading challenges in multi-rail computing, industrial automation, and infrastructure systems.
FAQ
What is the maximum bus capacitance supported by the TCA9801DGKR on the B-side?
The TCA9801DGKR supports up to 400 pF of total capacitance on the B-side (SDAB and SCLB pins). This value is specified in the Electrical Characteristics table under CBUS parameter and is critical for maintaining rise time and signal integrity at 400 kHz operation. Exceeding 400 pF may cause timing violations or communication failures. The A-side has no defined capacitance limit.
Can external pull-up resistors be used on the SDAB or SCLB pins of the TCA9801DGKR?
No - external pull-up resistors must not be connected to SDAB or SCLB. The TCA9801DGKR integrates a 1.1 mA current source on the B-side specifically to replace them. Adding external pull-ups violates the IEXT-I specification (≤200 µA), risks false low detection, and compromises the IILC-based contention resolution that ensures reliable clock stretching and arbitration.
Does the TCA9801DGKR require specific power sequencing between VCCA and VCCB?
No - the TCA9801DGKR has no power sequencing requirements. VCCA may power up before, after, or simultaneously with VCCB, and either supply may be greater than, less than, or equal to the other. This is enabled by independent UVLO circuits and isolated internal domains, eliminating system-level sequencing complexity in multi-rail designs.
What happens to the SCLA and SDAA pins when VCCA is unpowered but VCCB is active?
When VCCA falls below its UVLO threshold (0.3–0.55 V) while VCCB remains powered, the SCLA and SDAA pins enter a high-impedance state. They remain electrically safe and do not back-power VCCA. Meanwhile, SDAB and SCLB remain active via the B-side current source, allowing continued B-side communication independent of A-side supply status.
How does the TCA9801DGKR handle clock stretching and multi-master arbitration?
The TCA9801DGKR fully supports clock stretching and multi-master arbitration by preserving I²C bus electrical behavior - including open-drain signaling, bidirectional data flow, and dynamic contention detection. Its true buffering architecture (not pass-FET) maintains signal polarity and timing integrity, and its B-side current source enables accurate low-level detection during handoff events without overshoot or glitches.
TCA9801DGKR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Translator Type:
- Voltage Level
- Channel Type:
- Bidirectional
- Number of Circuits:
- 1
- Channels per Circuit:
- 2
- Voltage - VCCA:
- 0.8 V ~ 3.6 V
- Voltage - VCCB:
- 1.65 V ~ 3.6 V
- Input Signal:
- -
- Output Signal:
- -
- Output Type:
- Non-Inverted
- Data Rate:
- -
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Features:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
TCA9801DGKR FAQ
1.How can I place an order for TCA9801DGKR through Aetrix?
Please submit a Request for Quotation (RFQ) for TCA9801DGKR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TCA9801DGKR reliable?
The price and inventory of TCA9801DGKR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TCA9801DGKR is usually 5 days.
3.What payment methods are accepted for TCA9801DGKR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TCA9801DGKR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TCA9801DGKR?
TCA9801DGKR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TCA9801DGKR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TCA9801DGKR?
For technical support, including TCA9801DGKR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TCA9801DGKR requirements.
6.How does Aetrix verify that TCA9801DGKR is sourced from the original manufacturer or authorized distributors?
All TCA9801DGKR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TCA9801DGKR meets industry standards.
7.What is the process for return or replacement of TCA9801DGKR?
All TCA9801DGKR units undergo pre-shipment inspection (PSI). If there is an issue with TCA9801DGKR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TCA9801DGKR part is unused and in its original packaging.
Return procedure for TCA9801DGKR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
TCA9801DGKR Tags

-
74LVC1T45GW,125
Nexperia USA Inc.
-
74LVCH2T45DC,125
Nexperia USA Inc.

-
SN74LVC1T45DBVR
Texas Instruments

-
SN74LVC1T45DRLR
Texas Instruments

-
SN74LVC1T45DPKR
Texas Instruments

-
SN74LVC2T45DCTR
Texas Instruments

-
74LVC2T45GT,115
Nexperia USA Inc.

-
SN74LVC1T45YZPR
Texas Instruments

-
LSF0102DCUR
Texas Instruments

-
SN74LVC1T45DCKR
Texas Instruments

-
TXS0102DCTR
Texas Instruments

-
FXLP34P5X
onsemi
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
