Texas Instruments TCA9802DGKT

Overview

TCA9802DGKT from Texas Instruments is a dual-channel bidirectional I²C/SMBus level-translating buffer with integrated 2.2 mA current source on the B-side, enabling resistorless B-side pull-up, ultra-low power operation (≤7 µA A-side quiescent current at 0.8 V), and true buffering without static voltage offset (VOL ≈ 0.13 V on A-side, 0.26 V on B-side). It supports asymmetric supply rails (VCCA = 0.8–3.6 V, VCCB = 1.65–3.6 V) and is used in server backplanes to isolate high-speed I²C segments across voltage domains.

For engineers reviewing the TCA9802DGKT datasheet, TCA9802DGKT pinout, TCA9802DGKT application, or TCA9802DGKT equivalent, key selection criteria include B-side current source strength (2.2 mA), bus capacitance limit (400 pF), propagation delay (75–260 ns), UVLO thresholds (VCCA: 0.55 V, VCCB: 1.51 V), and absence of external B-side pull-up resistors.

Technical Context

The TCA9802DGKT implements true bidirectional buffering-not passive FET translation-using an internal current-source-based detection mechanism on the B-side to determine bus state without static voltage offset. This architecture enables low VOL on both sides and eliminates false-low latching during clock stretching.

It supports full I²C protocol features including multi-master arbitration and clock stretching, with independent enable control (EN referenced to VCCA) and powered-off high-impedance A-side pins. No power sequencing is required: VCCA may be greater than, less than, or equal to VCCB.

Key Specifications

Pinout & Package

Package: VSSOP-8 (DGK), 3.00 mm × 3.00 mm body size, 0.65 mm pitch.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar I²C level-shifting applications.

Compared with TCA9801DGKT and TCA9803DGKT, the TCA9802DGKT delivers optimal balance of B-side drive (2.2 mA), power efficiency (60 µA ICCB at 1.8 V), and 400 pF bus support - making it the default choice for mainstream server, industrial, and embedded I²C isolation where moderate slave count and noise immunity are required.

Availability

TCA9802DGKT is available at Aetrix Electronics and suitable for server backplanes, industrial controllers, and power-sensitive edge gateways requiring stable component supply, long-term lifecycle assurance, and guaranteed traceable sourcing.

Supply support for TCA9802DGKT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company specializing in analog and embedded processing technologies, with leadership in interface, power management, and signal chain solutions.

The TCA9802DGKT belongs to TI's I²C level-shifting buffer family, designed specifically to solve voltage-domain interoperability in high-reliability computing and industrial systems where traditional resistor-based or offset-based translators fail under timing or noise stress.

FAQ

What is the maximum supported bus capacitance on the B-side of the TCA9802DGKT?

The TCA9802DGKT supports up to 400 pF of total capacitance on the B-side (SDAB and SCLB pins combined), as specified in the Electrical Characteristics table. Exceeding this limit degrades rise time and may cause timing violations in 400 kHz Fast-mode I²C operation. The A-side has no defined capacitance limit. This 400 pF rating directly enables connection to up to 10–12 standard I²C slaves on the B-side, depending on trace length and package parasitics.

Can external pull-up resistors be used on the B-side pins (SDAB/SCLB) of the TCA9802DGKT?

No - external pull-up resistors must not be used on SDAB or SCLB. The TCA9802DGKT integrates a 2.2 mA current source on the B-side specifically to eliminate them. Adding external pull-ups violates the IEXT-I specification (max ±200 µA), risks false-low detection due to current contention, and prevents proper low-level recognition by violating the IILC (800 µA) and RILC (150 Ω) requirements. The device relies solely on its internal current source for B-side pull-up.

Does the TCA9802DGKT support clock stretching and multi-master arbitration?

Yes, the TCA9802DGKT fully supports clock stretching and multi-master arbitration as required by the I²C specification. Its true buffering architecture - unlike pass-FET translators - preserves bus timing relationships and avoids introducing static voltage offsets that could disrupt arbitration resolution or stretch acknowledgment timing. This is confirmed in Section 9.3.7 and the Functional Block Diagram of the official datasheet SCPS266B.

What happens to the A-side pins (SCLA/SDAA) when VCCA is unpowered but VCCB remains active?

When VCCA falls below its UVLO threshold (0.55 V), the SCLA and SDAA pins enter a powered-off high-impedance state, electrically isolating the A-side bus. This prevents back-powering or contention on the A-side while the B-side remains fully operational - a critical feature for hot-swap and partial-power-down scenarios. The B-side pins (SDAB/SCLB) remain active via VCCB and their internal current source.

Is there a power sequencing requirement between VCCA and VCCB for the TCA9802DGKT?

No - the TCA9802DGKT imposes no power sequencing requirements. VCCA may be powered before, after, or simultaneously with VCCB, and VCCA may be greater than, less than, or equal to VCCB within their respective operating ranges (0.8–3.6 V and 1.65–3.6 V). This flexibility simplifies system power architecture design and eliminates risk of latch-up or undefined behavior during power transitions.