Toshiba Semiconductor and Storage TCD1209DG(8Z,W)
- Part No.:
- TCD1209DG(8Z,W)
- Manufacturer:
- Toshiba Semiconductor and Storage
- Category:
- Image Sensors, Camera
- Package:
- 22-CDIP (0.400", 10.16mm)
- Datasheet:
-
TCD1209DG(8Z,W).pdf
- Description:
- CCD IMAGE SENSOR - INTEGRATED CI
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
TCD1209DG(8Z,W) from Toshiba Electronic Devices & Storage Corporation is a 2048-element CCD linear image sensor with 14 μm × 14 μm photodiodes, 5 V two-phase clock operation, 12 V power supply, and 22-pin CERDIP package-designed for high-resolution document scanning across B4-size paper at 8 lines/mm.
For engineers reviewing the TCD1209DG(8Z,W) datasheet, TCD1209DG(8Z,W) pinout, TCD1209DG(8Z,W) application, or TCD1209DG(8Z,W) equivalent, key selection criteria include dark signal voltage (≤2.5 mV), dynamic range (2000), transfer efficiency (92–98%), PRNU (≤10%), and timing-critical pulse width constraints (e.g., SH pulse width 1000–1500 ns).
Technical Context
The TCD1209DG(8Z,W) implements a charge-coupled architecture with dedicated transfer clocks (φ1, φ2, φ2B), reset (RS), clamp (CP), and shift gate (SH) control signals to serially read out integrated photodiode charge. Its PN photodiode array delivers high sensitivity (31 V/(lx·s) typ.) and low dark current under 25°C operation.
Operation requires precise 5 V logic-level clock pulses synchronized with 12 V analog supply (VOD), where timing margins are critical: φ1/φ2 cross-point delay ≤17 ns, RS pulse width 10–100 ns, and video data delay t11 = 15 ns typ. All voltages referenced to SS (ground) pin.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Image elements | 2048 pixels in single row-enables full-width B4 paper coverage at 8 lines/mm resolution |
| Pixel pitch | 14 μm center-to-center-defines optical sampling density and minimum resolvable feature size |
| Saturation exposure | 0.06 lx·s typ.-determines maximum incident light before pixel saturation in daylight fluorescent illumination |
| Dynamic range | 2000 typ.-ratio of saturation output (2.0 V) to dark signal (1.0 mV avg.), enabling wide scene luminance capture |
| Total transfer efficiency | 92–98%-quantifies charge retention during serial register transfer; impacts SNR and linearity |
| Random noise | 0.6 mV σ typ.-measured as ΔV standard deviation between adjacent dark pixels, limiting low-light detectability |
| DC output signal voltage | 5.5 V typ.-baseline video output level referenced to SS, requiring compatible ADC input range |
Pinout & Package
Package: 22-pin ceramic dual in-line package (CERDIP), WDIP22-G-400-2.54H footprint, glass window over active die area, rated for −25°C to +60°C operating temperature.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | OS | Video output signal-high-impedance analog voltage proportional to integrated photodiode charge |
| 2 | SS | Signal ground reference-common return for all analog and digital supplies and clocks |
| 3 | OD | Analog power supply-12 V supply for CCD vertical/horizontal registers and output amplifier |
| 5 | φ1 | Transfer clock phase 1-drives charge transfer from photodiodes into horizontal register |
| 6 | φ2 | Transfer clock phase 2-completes pixel-to-pixel charge transfer in horizontal register |
| 18 | RS | Reset gate-clears floating diffusion node prior to signal sampling; 10–100 ns pulse width required |
| 21 | CP | Clamp gate-establishes DC baseline for OS signal during clamping interval; timing-critical relative to φ2B |
| 22 | SH | Shift gate-controls horizontal charge transfer timing; 1000–1500 ns pulse width ensures full pixel shift |
Key Features
| Feature | Design Value |
|---|---|
| High-sensitivity PN photodiode array | 31 V/(lx·s) typical sensitivity enables reliable capture under low-intensity daylight fluorescent lighting |
| Low dark signal voltage | 1.0 mV typical dark output reduces fixed-pattern noise and extends usable integration time |
| Two-phase 5 V clock interface | Compatible with standard TTL/CMOS logic drivers-eliminates need for level-shifting circuitry |
| 2048-pixel linear resolution | Supports ≥200 DPI scanning at B4 paper width (257 mm), meeting mid-range document scanner requirements |
| Controlled PRNU | ≤10% photo response non-uniformity ensures consistent grayscale reproduction across full scan line |
Applications
| Document Scanner | Barcode Reader |
|---|---|
|
Use Scenario: High-speed A4/B4 flatbed or sheet-fed document digitization in office multifunction printers. IC Role / Device Role / Timing Role: Primary optical sensing element capturing reflected light line-by-line; driven by precisely timed φ1/φ2/SH/RS pulses. Use Value: 2048-pixel resolution and 8 lines/mm coverage enable 200+ DPI output without interpolation; low dark signal supports fast 10 ms integration. |
Use Scenario: Fixed-mount industrial barcode verification systems reading 1D codes on moving packaging lines. IC Role / Device Role / Timing Role: Linear light capture device synchronized to conveyor speed; OS signal fed to comparator-based decode ASIC. Use Value: 14 μm pixel pitch resolves narrow bar/space elements down to Code 39 or EAN-13 spec; dynamic range >2000 accommodates variable label reflectivity. |
| OCR Engine Sensor | Fax Machine Imaging |
|
Use Scenario: Embedded OCR modules in portable scanning pens or kiosk-based ID document readers. IC Role / Device Role / Timing Role: Analog front-end for character segmentation; OS output digitized by external 12-bit ADC with 15 ns data delay alignment. Use Value: 0.6 mV random noise and ≤10% PRNU ensure clean binarization thresholds; compact CERDIP package fits space-constrained handheld PCBs. |
Use Scenario: Legacy G3 fax machine imaging subsystems requiring analog line-scan output compatible with TI TMC2000-series modems. IC Role / Device Role / Timing Role: Direct replacement for discontinued linear CCDs; outputs composite video waveform synchronized to ITU-T T.30 timing. Use Value: DC output signal voltage (5.5 V typ.) matches legacy fax ADC input ranges; 12 V/5 V dual-supply interface preserves existing power architecture. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar linear CCD image sensor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TCD1208DG | 2048-element variant with identical pinout and 14 μm pitch but lower sensitivity (28 V/(lx·s) typ.) and higher dark signal (1.5 mV typ.) | Acceptable for cost-sensitive scanners where ambient light is controlled; not recommended for low-light barcode reading | Select TCD1208DG only if system-level SNR budget allows ≥3 dB degradation versus TCD1209DG(8Z,W) |
| KAI-02150 | 2152-pixel CMOS linear sensor with on-chip ADC, LVDS output, and 3.3 V operation-no external clocks or 12 V supply required | Enables simplified digital interface but requires redesign of timing controller and power delivery; incompatible with analog video chain | Choose KAI-02150 only when migrating to fully digital architecture and accepting PCB layout changes |
Compared with TCD1209DG(8Z,W), TCD1208DG offers identical mechanical and electrical compatibility at reduced optical performance, while KAI-02150 replaces analog CCD operation with integrated digital conversion-requiring new firmware, clocking, and power design but eliminating analog noise sensitivity.
Availability
TCD1209DG(8Z,W) is available at Aetrix Electronics and suitable for document scanning, industrial barcode verification, OCR engine development, and legacy fax imaging requiring stable component supply and long-lifecycle support.
Supply support for TCD1209DG(8Z,W) includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Toshiba Electronic Devices & Storage Corporation designs and manufactures discrete semiconductors, power devices, and imaging sensors with focus on industrial reliability and optical precision.
The TCD1209DG(8Z,W) belongs to Toshiba's linear CCD image sensor product line, engineered specifically for high-fidelity monochrome document capture in office automation and industrial inspection equipment.
FAQ
What is the operating power supply requirement for the TCD1209DG(8Z,W)?
The TCD1209DG(8Z,W) requires a 12 V analog power supply (VOD) for its CCD registers and output amplifier, and 5 V logic-level pulses for φ1, φ2, SH, RS, and CP clocks. Per datasheet Rev.2.4, VOD must be maintained between 11.4 V and 13.0 V for guaranteed performance; exceeding 15.0 V risks permanent damage. The TCD1209DG(8Z,W) draws up to 400 mW under typical conditions.
Does the TCD1209DG(8Z,W) include on-chip analog-to-digital conversion?
No, the TCD1209DG(8Z,W) is an analog-output CCD sensor: its OS pin delivers a continuous voltage waveform proportional to integrated photodiode charge, requiring external amplification and digitization. It contains no ADC, memory, or digital interface logic. System designers must provide a separate 12-bit or higher ADC with sampling aligned to the 15 ns video data delay (t11) specified in the TCD1209DG(8Z,W) timing chart.
What is the significance of the "8Z,W" suffix in TCD1209DG(8Z,W)?
The "8Z,W" suffix denotes Toshiba's internal package and screening variant: "8Z" specifies the WDIP22-G-400-2.54H 22-pin CERDIP package with 2.54 mm lead pitch and glass window, while "W" indicates compliance with Toshiba's standard industrial-grade reliability screening (including extended temperature validation and humidity testing). This suffix distinguishes it from bare-die or alternate-package versions of the same core die.
How does dark signal non-uniformity (DSNU) affect TCD1209DG(8Z,W) performance in scanning applications?
DSNU in the TCD1209DG(8Z,W) is specified at ≤2.5 mV peak-to-peak, representing pixel-to-pixel variation in thermal dark current. In scanning systems, uncorrected DSNU manifests as fixed-pattern noise-visible as faint horizontal bands in uniform-field captures. System-level correction requires per-pixel offset calibration using dark-frame subtraction; the TCD1209DG(8Z,W)'s low 1.0 mV typical dark signal simplifies this calibration and improves stability over temperature.
Can the TCD1209DG(8Z,W) operate at clock frequencies above 1 MHz?
Yes-the TCD1209DG(8Z,W) supports clock frequencies up to 20 MHz per the datasheet, though optimal optical performance (e.g., PRNU, dynamic range) is characterized at 1 MHz. At higher frequencies, transfer efficiency may decrease below 92%, and random noise may rise due to incomplete charge transfer. For applications demanding maximum SNR-such as high-accuracy OCR-the TCD1209DG(8Z,W) should be operated at or near its 1 MHz typ. clock frequency.
TCD1209DG(8Z,W) Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Toshiba Semiconductor and Storage
- Series:
- -
- Package/Case:
- 22-CDIP (0.400", 10.16mm)
- Packaging:
- Tray
- Product Status:
- Obsolete
- Type:
- CCD
- Pixel Size:
- 14µm x 14µm
- Active Pixel Array:
- -
- Frames per Second:
- -
- Voltage - Supply:
- 5V ~ 12V
- Supplier Device Package:
- 22-CDIP
- Operating Temperature:
- -
- Grade:
- -
- Qualification:
- -
TCD1209DG(8Z,W) FAQ
1.How can I place an order for TCD1209DG(8Z,W) through Aetrix?
Please submit a Request for Quotation (RFQ) for TCD1209DG(8Z,W) on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TCD1209DG(8Z,W) reliable?
The price and inventory of TCD1209DG(8Z,W) are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TCD1209DG(8Z,W) is usually 5 days.
3.What payment methods are accepted for TCD1209DG(8Z,W)?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TCD1209DG(8Z,W) transactions.
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4.How is shipping managed for TCD1209DG(8Z,W)?
TCD1209DG(8Z,W) orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TCD1209DG(8Z,W) order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TCD1209DG(8Z,W)?
For technical support, including TCD1209DG(8Z,W) datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TCD1209DG(8Z,W) requirements.
6.How does Aetrix verify that TCD1209DG(8Z,W) is sourced from the original manufacturer or authorized distributors?
All TCD1209DG(8Z,W) products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TCD1209DG(8Z,W) meets industry standards.
7.What is the process for return or replacement of TCD1209DG(8Z,W)?
All TCD1209DG(8Z,W) units undergo pre-shipment inspection (PSI). If there is an issue with TCD1209DG(8Z,W), returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TCD1209DG(8Z,W) part is unused and in its original packaging.
Return procedure for TCD1209DG(8Z,W):
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
TCD1209DG(8Z,W) Tags

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MT9M114EBLSTCZ-CR
onsemi

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EPC611-CSP24-001
ESPROS Photonics AG

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AR0147ATSC00XUEG5-DRBR
onsemi

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AR0130CSSM00SPCA0-DRBR
onsemi

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AR1335CSSC11SMKA0-CP
onsemi
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AR0521SR2M09SURA0-DP
onsemi
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AR0135CS2M25SUEA0-DPBR
onsemi

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AR0522SRSC09SURA0-DP
onsemi

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AR0134CSSC00SPCA0-DPBR
onsemi

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AR0134CSSM00SUEA0-DPBR
onsemi
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AR0521SR2C09SURA0-DP
onsemi
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AR0135CS2M00SUEA0-DPBR
onsemi
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