Toshiba Semiconductor and Storage TCD1304DG(8Z,K)
- Part No.:
- TCD1304DG(8Z,K)
- Manufacturer:
- Toshiba Semiconductor and Storage
- Category:
- Image Sensors, Camera
- Package:
- 22-CDIP (0.400", 10.16mm)
- Datasheet:
-
TCD1304DG(8Z,K).pdf
- Description:
- CCD LINEAR IMAGE SENSOR WDIP22
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
TCD1304DG(8Z,K) from Toshiba Electronic Devices & Storage Corporation is a 3648-element CCD linear image sensor with 8 μm × 200 μm photosensitive elements, electronic shutter (ICG) function, and integrated sample-and-hold circuitry. It delivers high sensitivity (160 V/lx·s typ.), low dark signal (2 mV typ.), and 300:1 dynamic range for precision optical scanning in spectrometry and industrial inspection systems.
For engineers reviewing the TCD1304DG(8Z,K) datasheet, TCD1304DG(8Z,K) pinout, TCD1304DG(8Z,K) application, or TCD1304DG(8Z,K) equivalent, key selection considerations include integration time control via ICG timing (tINT ≥ 10 μs), 2.0 MHz master clock support, CERDIP-22 package compatibility, and analog/digital dual-supply operation at 4.0 V.
Technical Context
The TCD1304DG(8Z,K) integrates two parallel CCD analog shift registers driven by independent SH and ICG clocks, enabling precise exposure control and pixel charge transfer with 95% total transfer efficiency. Its PN photodiode sensing region provides spectral response optimized for visible light, with PRNU ≤ 10% and register imbalance ≤ 3% under uniform illumination.
Operation requires synchronized master clock (fφM = 0.8–4.0 MHz), shift gate (VSH = 3.0–5.5 V), and integration clear gate (VICG = 3.0–5.5 V) signals referenced to SS (ground). Output signal (OS) is buffered DC-coupled analog voltage (1.5–3.5 V) with 0.5 kΩ typical output impedance.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Image Elements | 3648 effective pixels + 62 dummy/light-shielded pixels; enables full-line spectral acquisition without interpolation |
| Sensitivity | 160 V/lx·s typ.; supports low-light detection down to 0.004 lx·s saturation exposure |
| Dynamic Range | 300:1 typ.; determined by VSAT (600 mV) / VMDK (2 mV); scales inversely with integration time |
| Dark Signal | 2 mV typ. at Ta = 25°C; limits minimum detectable signal in long-integration applications |
| Master Clock | 2.0 MHz typ. (up to 4.0 MHz at VAD = VDD ≥ 4.0 V); sets maximum line readout rate of ~0.5 MHz |
| Output Voltage | 2.5 V typ. DC output (VOS) with 1.0 kΩ max output impedance; interfaces directly with 12-bit ADCs |
| Operating Temp | −25°C to +60°C; validated performance across industrial ambient ranges without active cooling |
Pinout & Package
Package: 22-pin CERDIP (WDIP22-G-400-2.54H), hermetically sealed ceramic dual-in-line with glass window for optical access. Lead pitch 2.54 mm, body width 15.24 mm, height 4.7 mm.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | VDD | Digital power supply (3.0–5.5 V); powers logic and clock drivers; must be decoupled near pin |
| 2 | VAD | Analog power supply (3.0–5.5 V); powers CCD registers and output buffer; separate from VDD for noise isolation |
| 3 | ICG | Integration Clear Gate input; TTL/CMOS-compatible pulse initiates exposure reset; t1 delay 1–5 μs |
| 4 | φM | Master clock input; drives internal CCD timing; 0.8–4.0 MHz operation; capacitance 10 pF |
| 5 | SH | Shift gate input; controls charge transfer from photodiodes to analog shift register; t3 width ≥ 1 μs |
| 21 | OS | Analog output signal; DC-coupled voltage proportional to incident light; 0.5–1.0 kΩ output impedance |
| 22 | SS | Signal ground reference; all voltages defined relative to this pin; must connect to low-impedance system ground |
Key Features
| Feature | Design Value |
|---|---|
| Electronic Shutter (ICG) | Enables precise, variable integration time (≥10 μs) without mechanical components; eliminates motion blur in moving-scene capture |
| High Transfer Efficiency | 95% typ. total charge transfer; minimizes signal loss during pixel readout and preserves SNR across full 3648-pixel line |
| Low PRNU | ≤10% photo response non-uniformity; ensures pixel-to-pixel intensity consistency critical for quantitative spectral analysis |
| Integrated Sample-and-Hold | On-chip circuitry stabilizes output voltage during digitization; eliminates external S/H component and associated layout complexity |
| Optimized Spectral Response | Peak sensitivity in visible range (400–700 nm); reduced IR sensitivity mitigates resolution degradation from out-of-band light |
Applications
| UV-Vis Spectrophotometry | Laser Line Profiling |
|---|---|
|
Use Scenario: Measuring absorbance spectra of liquid samples across 200–800 nm using grating-dispersed light. IC Role / Device Role / Timing Role: Linear image sensor capturing dispersed spectrum; ICG timing sets integration to match lamp intensity and detector saturation limits. Use Value: 3648-pixel resolution enables <0.1 nm wavelength resolution; low dark current (2 mV) ensures accurate baseline subtraction in low-intensity UV bands. |
Use Scenario: Real-time monitoring of laser beam shape, width, and centroid position in semiconductor lithography tools. IC Role / Device Role / Timing Role: High-speed line scan sensor triggered synchronously with laser pulse; SH/φM timing controls readout rate up to 0.5 MHz. Use Value: 8 μm pixel pitch resolves sub-10 μm beam features; electronic shutter eliminates motion artifacts from stage vibration or thermal drift. |
| Barcode & OCR Scanning | Industrial Surface Inspection |
|
Use Scenario: High-speed reading of 1D/2D barcodes on moving packaging lines at conveyor speeds >2 m/s. IC Role / Device Role / Timing Role: Linear sensor capturing reflected LED-illuminated barcode; ICG pulse defines exposure to suppress ambient light interference. Use Value: 300:1 dynamic range handles variable reflectivity (matte vs. glossy surfaces); 2.0 MHz clock supports >10 kHz line rates for real-time decode. |
Use Scenario: Detecting micro-scratches, coating thickness variation, or solder paste defects on PCBs using structured lighting. IC Role / Device Role / Timing Role: Precision line sensor acquiring calibrated grayscale profiles; VOS stability (±0.5 V over temp) enables consistent defect thresholding. Use Value: 10% PRNU and 3% register imbalance ensure repeatable pixel-level intensity measurement; CERDIP package withstands reflow and cleaning solvents. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar linear CCD image sensor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TCD1304AP | Same 3648-element architecture but in 24-pin PDIP package; no glass window; lower sensitivity (120 V/lx·s typ.) | Used in cost-sensitive, non-optical-coupled applications where ambient light control is feasible | Select TCD1304AP only if mechanical mounting constraints prohibit CERDIP or optical window requirements are absent |
| KAI-0340-CR | 3.4 MP interline CCD (not linear); 10-bit digital LVDS output; requires external timing generator and power sequencing | Targeted at area-scan machine vision, not line-scan spectroscopy or profiling | Choose KAI-0340-CR only when 2D imaging is required and system can accommodate complex clocking and digital interface overhead |
Compared with TCD1304AP and KAI-0340-CR, the TCD1304DG(8Z,K) uniquely combines hermetic optical access, integrated analog output buffering, and electronic shutter control in a single CERDIP-22 package-enabling direct replacement of legacy linear scanners without redesigning optics or timing firmware.
Availability
TCD1304DG(8Z,K) is available at Aetrix Electronics and suitable for UV-Vis spectrophotometry, laser line profiling, and industrial surface inspection requiring stable component supply, long-term lifecycle support, and traceable sourcing for OEM production programs.
Supply support for TCD1304DG(8Z,K) includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Toshiba Electronic Devices & Storage Corporation designs high-reliability semiconductor components for industrial, automotive, and consumer applications, with core expertise in analog, power, and imaging devices.
The TCD1304DG(8Z,K) belongs to Toshiba's linear CCD image sensor product line, engineered specifically for high-precision optical measurement systems requiring stable analog output, low noise, and deterministic exposure control.
FAQ
What is the minimum integration time supported by the TCD1304DG(8Z,K) electronic shutter function?
The TCD1304DG(8Z,K) supports a minimum integration time (tINT) of 10 μs when using the ICG pulse for electronic shutter control. This value is specified in the Timing Requirements section of the datasheet and assumes proper synchronization between ICG and SH pulses. Shorter integration times risk incomplete charge transfer and increased image lag. The TCD1304DG(8Z,K) achieves this timing through dedicated ICG circuitry that resets photodiode wells before readout begins.
Does the TCD1304DG(8Z,K) require separate analog and digital power supplies, and what are their voltage ranges?
Yes, the TCD1304DG(8Z,K) requires two independent power supplies: VAD (analog) and VDD (digital), both rated from 3.0 V to 5.5 V per the Recommended Operating Conditions table. VAD powers the CCD registers and output buffer, while VDD supplies the logic and clock drivers. Although the datasheet permits VAD = VDD, best practice is to use separate filtered rails to minimize digital switching noise coupling into the analog signal path of the TCD1304DG(8Z,K).
How many effective pixels does the TCD1304DG(8Z,K) provide, and what is the purpose of the dummy outputs?
The TCD1304DG(8Z,K) provides 3648 effective image sensing elements, plus 62 additional pixels designated as dummy or light-shielded outputs. These include 16 leading dummy outputs, 13 light-shielded outputs, 3 trailing dummy outputs, and 14 final dummy outputs - totaling 3694 pixels per line readout. The dummy outputs stabilize CCD clocking transients and provide reference levels for black-level correction, ensuring consistent DC output voltage (VOS) across the active 3648-pixel array of the TCD1304DG(8Z,K).
What is the spectral response limitation of the TCD1304DG(8Z,K), and why is infrared light problematic?
The TCD1304DG(8Z,K) exhibits peak sensitivity in the visible range (400–700 nm), with reduced response beyond 700 nm. Infrared light degrades resolution and photo response non-uniformity (PRNU) because it penetrates deeper into the silicon substrate, causing lateral charge diffusion that blurs pixel boundaries. The datasheet cautions against unfiltered IR illumination to maintain the TCD1304DG(8Z,K)'s specified 10% PRNU and spatial fidelity in precision optical applications.
Can the TCD1304DG(8Z,K) be soldered using standard reflow processes, and what is the recommended method?
No, the TCD1304DG(8Z,K) must not be soldered using solder flow (wave) or reflow methods due to thermal and mechanical stress risks to the glass window and ceramic package. The manufacturer specifies hand-soldering with a soldering iron at ≤350°C for ≤3 seconds per lead. This constraint is explicitly stated in the Cautions section to prevent window soiling, cracking, or internal delamination - critical for maintaining the optical integrity and long-term reliability of the TCD1304DG(8Z,K).
TCD1304DG(8Z,K) Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Toshiba Semiconductor and Storage
- Series:
- -
- Package/Case:
- 22-CDIP (0.400", 10.16mm)
- Packaging:
- Tray
- Product Status:
- Active
- Type:
- CCD
- Pixel Size:
- 8µm x 200µm
- Active Pixel Array:
- -
- Frames per Second:
- -
- Voltage - Supply:
- 3V ~ 5.5V
- Supplier Device Package:
- 22-CERDIP
- Operating Temperature:
- -25°C ~ 60°C
- Grade:
- -
- Qualification:
- -
TCD1304DG(8Z,K) FAQ
1.How can I place an order for TCD1304DG(8Z,K) through Aetrix?
Please submit a Request for Quotation (RFQ) for TCD1304DG(8Z,K) on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TCD1304DG(8Z,K) reliable?
The price and inventory of TCD1304DG(8Z,K) are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TCD1304DG(8Z,K) is usually 5 days.
3.What payment methods are accepted for TCD1304DG(8Z,K)?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TCD1304DG(8Z,K) transactions.
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4.How is shipping managed for TCD1304DG(8Z,K)?
TCD1304DG(8Z,K) orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TCD1304DG(8Z,K) order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TCD1304DG(8Z,K)?
For technical support, including TCD1304DG(8Z,K) datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TCD1304DG(8Z,K) requirements.
6.How does Aetrix verify that TCD1304DG(8Z,K) is sourced from the original manufacturer or authorized distributors?
All TCD1304DG(8Z,K) products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TCD1304DG(8Z,K) meets industry standards.
7.What is the process for return or replacement of TCD1304DG(8Z,K)?
All TCD1304DG(8Z,K) units undergo pre-shipment inspection (PSI). If there is an issue with TCD1304DG(8Z,K), returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TCD1304DG(8Z,K) part is unused and in its original packaging.
Return procedure for TCD1304DG(8Z,K):
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
TCD1304DG(8Z,K) Tags

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MT9M114EBLSTCZ-CR
onsemi

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EPC611-CSP24-001
ESPROS Photonics AG

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AR0147ATSC00XUEG5-DRBR
onsemi

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AR0130CSSM00SPCA0-DRBR
onsemi

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AR1335CSSC11SMKA0-CP
onsemi
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AR0521SR2M09SURA0-DP
onsemi
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AR0135CS2M25SUEA0-DPBR
onsemi

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AR0522SRSC09SURA0-DP
onsemi

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AR0134CSSC00SPCA0-DPBR
onsemi

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AR0134CSSM00SUEA0-DPBR
onsemi
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AR0521SR2C09SURA0-DP
onsemi
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AR0135CS2M00SUEA0-DPBR
onsemi
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