My Inquiry
My Account
Toshiba Semiconductor and Storage TCK302G,LF
- Part No.:
- TCK302G,LF
- Manufacturer:
- Toshiba Semiconductor and Storage
- Package:
- 9-UFBGA, WLCSP
- Datasheet:
-
TCK302G,LF.pdf
- Description:
- IC PWR SWITCH N-CHAN 1:1 9WCSP
- Quantity:
- Payment:
- Shipping:
Inventory:1,225
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
TCK302G,LF from Toshiba is a 28 V high-input-voltage single-input–single-output load switch IC with overvoltage lockout (OVLO) set to 10.5 V (typ.), 73 mΩ typical ON resistance at 4.5 V/−1.0 A, and reverse current blocking capability. It integrates thermal shutdown, FLAG output, slew-rate-controlled turn-on, and inrush current reduction-designed for battery charge management and portable power rail control.
For engineers reviewing the TCK302G,LF datasheet, TCK302G,LF pinout, TCK302G,LF application, or TCK302G,LF equivalent, this page delivers verified electrical parameters, WCSP9 package layout, functional differences among TCK301G/TCK302G/TCK303G variants, and real-world use cases in compact battery-powered systems requiring precise input voltage supervision and low-loss power switching.
Technical Context
The TCK302G,LF implements a monolithic N-channel MOSFET power switch with integrated charge pump, UVLO (2.9 V typ.) and OVLO (10.5 V typ.) comparators, and open-drain FLAG output that asserts high-impedance during fault conditions-including overvoltage, undervoltage, or thermal shutdown. Its CE and VCT pins support active-low enable and active-high control logic with internal 530 kΩ pull-up resistors.
It features reverse current blocking when switched off, 15 ms internal startup hold time, and AC timing specifications including 2 ms VOUT rise time (CL = 1.0 µF), 0.12 ms fall time, and sub-microsecond VCT disable delay. Thermal shutdown triggers at junction temperature ≥150 °C and releases after cooldown.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Max Input Voltage | 28 V - supports wide-range industrial and battery-derived rails up to Li-ion stack + margin. |
| OVLO Threshold | 10.5 V (typ.), 9.1–11.9 V (min–max) - protects downstream circuitry from overvoltage events in 12 V nominal systems. |
| ON Resistance | 73 mΩ (typ.) at VIN = 4.5 V, IOUT = −1.0 A - limits conduction loss to <73 mW at 1 A, enabling efficient power delivery. |
| Output Current | 3.0 A DC - sustains continuous load current for USB PD, PMIC input staging, or battery charging paths. |
| FLAG Output | Open-drain, active-high when VIN within UVLO/OVLO window - provides system-level fault indication without external pull-up. |
| Package Thermal Rating | PD = 1.65 W on 4-layer FR4 (40 mm × 40 mm) - defines maximum steady-state power dissipation under standard PCB layout. |
| Startup Hold Time | 15 ms internal delay - prevents premature output activation during input ramp-up, reducing inrush stress. |
Pinout & Package
Delivered in ultra-compact WCSP9 package (1.5 mm × 1.5 mm, 0.5 mm pitch, 0.5 mm typical thickness), optimized for high-density portable PCBs such as smartphones and wearables.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A1 | FLAG | Open-drain status output; high-impedance during OVLO, UVLO, or thermal shutdown - enables fault-aware system sequencing. |
| A2 | VCT | Active-high switch control input with internal 530 kΩ pull-up - allows direct MCU GPIO drive without external resistor. |
| A3 | CE | Active-low chip enable with internal 530 kΩ pull-down - supports hardware-level power gating and failsafe disable. |
| B1, C1 | VIN | Main power input with integrated OVLO/UVLO comparators - accepts 2.3–28 V and blocks operation outside safe window. |
| B2, C2 | GND | Power ground reference for switch, logic, and protection circuits - requires low-impedance connection to minimize noise coupling. |
| B3, C3 | VOUT | Switched output node with reverse-current blocking when OFF - eliminates backfeed from downstream capacitors or loads. |
Key Features
| Feature | Design Value |
|---|---|
| Overvoltage Lockout | Configured at 10.5 V (typ.) - matches 12 V system rail tolerances and prevents damage to 5 V/3.3 V downstream ICs. |
| Inrush Current Reduction | Integrated slew-rate control - limits dV/dt at VOUT to reduce peak input capacitor stress and EMI during turn-on. |
| Reverse Current Blocking | Automatic activation when switch is OFF - eliminates need for external back-to-back FETs or diodes in bidirectional power paths. |
| Thermal Shutdown | Self-resetting protection at Tj ≥150 °C - maintains reliability under sustained overload or poor heatsinking without latch-up. |
| Low Quiescent Current | 130 µA (ON), 75 µA (OFF1), 1.3 µA (OFF2) - minimizes standby power loss in always-on battery systems. |
Applications
| USB-C Power Delivery Input Stage | Smartphone Battery Charging Path |
|---|---|
|
Use Scenario: Managing power from variable USB-C sources (5–20 V) into a PMIC input rail while preventing overvoltage faults. IC Role / Device Role / Timing Role: Primary input load switch with OVLO set to 10.5 V - blocks >12 V inputs before they reach sensitive buck converters. Use Value: Eliminates need for discrete OVP IC and series FET, saving board space and BOM cost in tight smartphone bezels. |
Use Scenario: Isolating battery charger IC from main system rail during sleep mode to prevent leakage and self-discharge. IC Role / Device Role / Timing Role: Low-leakage (0.1 µA OFF-state) power gate with reverse-current blocking - ensures zero backfeed from battery to system when powered down. Use Value: Extends standby battery life by >15% in always-connected mobile devices through controlled rail isolation. |
| Industrial Sensor Node Power Sequencing | Portable Medical Device Power Management |
|
Use Scenario: Enabling clean power-up of analog front-end and MCU subsystems from a shared 24 V supply with strict voltage compliance. IC Role / Device Role / Timing Role: Supervised load switch with 15 ms startup hold and FLAG feedback - synchronizes power delivery with firmware initialization. Use Value: Prevents brown-out resets and analog sensor corruption by ensuring stable VOUT before system wake-up. |
Use Scenario: Safely routing power from rechargeable Li-ion battery to critical therapy circuitry while monitoring input health. IC Role / Device Role / Timing Role: Fault-aware power switch with thermal shutdown and OVLO - halts power delivery if battery pack overheats or experiences overvoltage. Use Value: Meets IEC 60601-1 safety requirements for patient-connected equipment via hardware-enforced power cutoff. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar load switch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS22916BLYFPR | Lower max VIN (5.5 V), no OVLO, smaller 1.0 mm × 1.0 mm DSBGA6 package, 44 mΩ RON | Suitable only for 3.3 V/5 V rails; lacks voltage supervision - requires external OVP for 12 V+ systems. | Select when operating strictly below 5.5 V and board area is more constrained than voltage protection needs. |
| RT9711CGQW | Higher OVLO (14 V), 85 mΩ RON, 5 V max VIN, SOT-23-6 package, no FLAG output | Compatible with 12 V systems but limited to lower input range; missing fault reporting interface for system diagnostics. | Choose where FLAG signal is unnecessary and thermal performance is less critical than cost-sensitive SOT-23 integration. |
Compared with TPS22916BLYFPR and RT9711CGQW, the TCK302G,LF uniquely combines 28 V input tolerance, 10.5 V OVLO, FLAG status signaling, and WCSP9 footprint - making it the only option among the three qualified for compact, high-voltage, fault-aware battery charge path designs.
Availability
TCK302G,LF is available at Aetrix Electronics and suitable for USB-C power delivery input stages, smartphone battery charging paths, and industrial sensor node power sequencing requiring stable component supply across extended temperature ranges (−40 to 85 °C) and long-lifecycle programs.
Supply support for TCK302G,LF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Toshiba Electronic Devices & Storage Corporation designs high-reliability analog and power ICs for consumer, industrial, and automotive markets, with emphasis on miniaturization, efficiency, and system-level protection.
The TCK302G,LF belongs to Toshiba's TCK30 series of high-voltage load switches - engineered specifically for space-constrained portable electronics needing robust input voltage supervision and reverse-current blocking without external components.
FAQ
What is the overvoltage lockout threshold for TCK302G,LF?
The TCK302G,LF has a factory-set overvoltage lockout (OVLO) threshold of 10.5 V (typical), with a guaranteed range of 9.1 V to 11.9 V across temperature. This value is fixed per device variant and cannot be adjusted externally - distinguishing it from TCK301G (6.6 V) and TCK303G (15.5 V). The OVLO function disables the internal FET and pulls FLAG to high-impedance when VIN exceeds this threshold.
Does TCK302G,LF support reverse current blocking, and how does it work?
Yes, TCK302G,LF provides automatic reverse current blocking when the main switch is turned OFF. This is achieved through the intrinsic body diode orientation and gate control of the internal N-channel MOSFET - preventing current flow from VOUT back to VIN. The feature operates without external components and remains active during CE = HIGH or VCT = LOW states, making it suitable for battery backup and dual-power-source applications.
What is the purpose of the FLAG pin on TCK302G,LF?
The FLAG pin on TCK302G,LF is an open-drain output that signals normal operation: it goes high-impedance during overvoltage, undervoltage, thermal shutdown, or CE deactivation. When VIN is within the safe window (2.9 V < VIN < 10.5 V) and the switch is enabled, FLAG is pulled high by an external resistor. This allows microcontrollers to monitor power integrity in real time - a key requirement for fail-safe sequencing in medical and industrial systems using TCK302G,LF.
Can TCK302G,LF operate from a 3.3 V input supply?
No - TCK302G,LF requires a minimum input voltage of 2.3 V to enable internal circuitry, but its UVLO rising threshold is 2.9 V (typical), meaning the device will not turn on until VIN exceeds ~2.9 V. At 3.3 V, it operates fully: RON is 73 mΩ (typ.), FLAG functions correctly, and all protections remain active. However, operation below 2.9 V results in forced shutdown and FLAG high-impedance state.
What package type and dimensions does TCK302G,LF use?
TCK302G,LF uses the WCSP9 (Wafer Chip Scale Package, 9-bump) format measuring 1.5 mm × 1.5 mm with 0.5 mm pitch and 0.5 mm typical thickness. It weighs 3.5 mg (typical) and is designed for fine-pitch reflow assembly on high-density PCBs. Land pattern dimensions and solder mask recommendations are provided in Toshiba's official package drawing (document TCK301G/TCK302G/TCK303G, page 10).
TCK302G,LF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Toshiba Semiconductor and Storage
- Package/Case:
- 9-UFBGA, WLCSP
- Series:
- TCK30
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Switch Type:
- General Purpose
- Number of Outputs:
- 1
- Ratio - Input:Output:
- 1:1
- Output Configuration:
- High Side
- Output Type:
- N-Channel
- Interface:
- On/Off
- Voltage - Load:
- 18V (Max)
- Voltage - Supply (Vcc/Vdd):
- 2.3V ~ 28V
- Current - Output (Max):
- 3A
- Rds On (Typ):
- 73mOhm
- Input Type:
- -
- Features:
- Slew Rate Controlled, Status Flag
- Fault Protection:
- Over Temperature, Over Voltage, Reverse Current, UVLO
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 9-WCSP (1.5x1.5)
TCK302G,LF FAQ
1.How can I place an order for TCK302G,LF through Aetrix?
Please submit a Request for Quotation (RFQ) for TCK302G,LF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TCK302G,LF reliable?
The price and inventory of TCK302G,LF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TCK302G,LF is usually 5 days.
3.What payment methods are accepted for TCK302G,LF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TCK302G,LF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TCK302G,LF?
TCK302G,LF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TCK302G,LF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TCK302G,LF?
For technical support, including TCK302G,LF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TCK302G,LF requirements.
6.How does Aetrix verify that TCK302G,LF is sourced from the original manufacturer or authorized distributors?
All TCK302G,LF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TCK302G,LF meets industry standards.
7.What is the process for return or replacement of TCK302G,LF?
All TCK302G,LF units undergo pre-shipment inspection (PSI). If there is an issue with TCK302G,LF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TCK302G,LF part is unused and in its original packaging.
Return procedure for TCK302G,LF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
TCK302G,LF Tags
-
TPS22919DCKR
Texas Instruments
-
MIC2091-1YM5-TR
Microchip Technology
-
MIC2090-1YM5-TR
Microchip Technology
-
TPS22995RZFR
Texas Instruments
-
TPS22975DSGR
Texas Instruments
-
SIP32510DT-T1-GE3
Vishay Siliconix
-
ULN2003D1013TR
STMicroelectronics
-
MIC2005A-1YM5-TR
Microchip Technology
-
MIC2005A-1YM6-TR
Microchip Technology
-
TPS22916BYFPR
Texas Instruments
-
TPS22917DBVR
Texas Instruments
-
ULN2003APWR
Texas Instruments
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
