Toshiba Semiconductor and Storage TCR3DM135,LF(SE
- Part No.:
- TCR3DM135,LF(SE
- Manufacturer:
- Toshiba Semiconductor and Storage
- Package:
- 4-UDFN Exposed Pad
- Datasheet:
-
TCR3DM135,LF(SE.pdf
- Description:
- LDO REG IOUT: 300MA VIN: 6V VOUT
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
TCR3DM135,LF(SE) from Toshiba Electronic Devices & Storage Corporation is a 1.35 V fixed-output CMOS low-dropout regulator with inrush current protection, delivering up to 300 mA output current, 390 mV typical dropout voltage at 300 mA, and 38 μVrms output noise - designed for power management in space-constrained portable electronics such as smartphone baseband ICs and PMIC subsystems.
For engineers reviewing the TCR3DM135,LF(SE) datasheet, TCR3DM135,LF(SE) pinout, TCR3DM135,LF(SE) application, or TCR3DM135,LF(SE) equivalent, key selection criteria include its ultra-small DFN4E (1.0 mm × 1.0 mm) package, guaranteed ±18 mV output voltage accuracy at 1.35 V, auto-discharge function, and compatibility with 1.0 μF ceramic input/output capacitors without external compensation.
Technical Context
The TCR3DM135,LF(SE) employs a CMOS pass transistor architecture enabling low quiescent current (65 μA typ. at 1.35 V output) and stable operation with minimal external components. Its integrated inrush current protection circuit limits peak input current during startup, while the auto-discharge function actively discharges the output capacitor when the CONTROL pin is pulled low.
This regulator features internal over-current and over-temperature protection, a dedicated CONTROL pin with defined ON/OFF thresholds (VCT(ON) ≥ 1.0 V, VCT(OFF) ≤ 0.4 V), and a center thermal pad that must be connected to GND for thermal performance - all optimized for battery-powered systems requiring fast load transient response (±80 mV typ.) and high ripple rejection (70 dB typ. at 1 kHz).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output voltage | Fixed 1.35 V ±18 mV (guaranteed accuracy enables direct powering of 1.35 V I/O domains without external feedback) |
| Max output current | 300 mA (supports single-core microcontrollers or RF front-end biasing without thermal derating at 25°C) |
| Dropout voltage | 390 mV typ. at 300 mA (allows regulation from 1.74 V input, compatible with single-cell Li-ion or Li-poly discharge profiles) |
| Output noise | 38 μVrms (10 Hz–100 kHz) (low enough for noise-sensitive analog/RF circuits like ADC references or PLL VCO supplies) |
| Load transient response | ±80 mV (1 mA ↔ 300 mA step, COUT = 1.0 μF) (minimizes voltage droop during processor wake-up bursts) |
| Ripple rejection | 70 dB typ. at 1 kHz (suppresses switching noise from upstream DC-DC converters feeding the LDO) |
| Quiescent current | 65 μA typ. at 1.35 V output (enables >1-year battery life in always-on sensor nodes) |
| Standby current | 0.1 μA typ. (CONTROL = 0 V) (supports ultra-low-power deep-sleep modes) |
Pinout & Package
TCR3DM135,LF(SE) uses the ultra-compact DFN4E package (1.0 mm × 1.0 mm × 0.58 mm height, 1.3 mg weight) with an exposed thermal pad on the bottom surface. The pad must be soldered to a GND copper area for thermal and electrical integrity.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VIN | Input supply connection | Accepts 1.75–5.5 V input; requires 1.0 μF ceramic capacitor placed within 2 mm for stability |
| VOUT | Regulated output node | Delivers fixed 1.35 V; connects directly to load; 1.0 μF ceramic capacitor required adjacent to pin |
| GND | Ground reference and thermal path | Primary ground return; center thermal pad must be connected to PCB GND plane for thermal dissipation |
| CONTROL | Enable/disable logic input | Active-high control: ≥1.0 V = ON, ≤0.4 V = OFF; internal pull-down ensures default OFF state |
Key Features
| Feature | Design Value |
|---|---|
| Inrush current protection | Prevents input voltage sag and system brownout during cold-start by limiting initial charge current into output capacitor |
| Auto-discharge function | Actively pulls VOUT to GND within milliseconds after CONTROL goes low, eliminating residual voltage that could cause latch-up in downstream logic |
| Ultra-small DFN4E package | 1.0 mm × 1.0 mm footprint saves >70% board area vs. SOT-23, enabling high-density mobile PCB layouts |
| Ceramic capacitor compatibility | Stable with 1.0 μF X5R/X7R ceramics (ESR < 10 Ω); eliminates need for larger, less reliable tantalum or aluminum electrolytics |
| Fast load transient response | ±80 mV deviation under 1 mA ↔ 300 mA dynamic load steps ensures clean supply for burst-mode processors and RF transceivers |
| Over-temperature shutdown | Thermal foldback activates at TJ ≈ 150°C, protecting device during sustained overload or poor heatsinking conditions |
Applications
| Smartphone Baseband Power | Wearable Sensor Hub Supply |
|---|---|
|
Use Scenario: Providing clean, low-noise 1.35 V supply to application processor I/O banks and memory interfaces in compact smartphones. IC Role / Device Role / Timing Role: Primary post-regulator for noise-sensitive digital I/O domains, decoupling switching noise from main PMIC buck converters. Use Value: 38 μVrms output noise and 70 dB ripple rejection prevent bit errors and timing jitter in high-speed data interfaces (e.g., LPDDR4 I/O). |
Use Scenario: Powering ultra-low-power motion sensor fusion hubs (accelerometer + gyroscope + MCU) in fitness trackers. IC Role / Device Role / Timing Role: Always-on LDO supplying real-time sensor data acquisition chain with minimal quiescent current. Use Value: 65 μA quiescent current and 0.1 μA standby enable multi-week battery life in coin-cell-powered devices. |
| IoT Edge Node PMIC Subsystem | Medical Patch Monitor Bias Rail |
|
Use Scenario: Generating stable 1.35 V bias for BLE SoC radio peripherals and secure element ICs in industrial IoT gateways. IC Role / Device Role / Timing Role: Secondary LDO in multi-rail PMIC architecture, activated only during wireless transmission bursts. Use Value: Fast 80 mV load transient response prevents RF packet loss during sudden current demand spikes from BLE transmitter activation. |
Use Scenario: Delivering regulated 1.35 V to analog front-end amplifiers and ADCs in disposable ECG patch monitors. IC Role / Device Role / Timing Role: Precision analog supply rail with tight output tolerance and low noise for medical-grade signal integrity. Use Value: ±18 mV output accuracy and 390 mV dropout ensure consistent amplifier gain and ADC reference stability across battery discharge cycle. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar low-noise, low-dropout regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R1190H135B-TR-FE | 1.35 V fixed output, 300 mA, 250 mV dropout (typ.), but no inrush current protection or auto-discharge | Lacks inrush control and active discharge - unsuitable for systems requiring controlled power sequencing or fast reset | Select if lowest possible dropout is critical and sequencing is handled externally |
| MCP1804T-135I/OT | 1.35 V fixed output, 150 mA max, 450 mV dropout (typ.), includes thermal shutdown but no inrush protection | Lower current rating and no auto-discharge limits use in higher-power or fast-wake-up applications | Select for cost-sensitive, lower-current designs where full 300 mA capability is not required |
Compared with R1190H135B-TR-FE and MCP1804T-135I/OT, the TCR3DM135,LF(SE) uniquely integrates inrush current limiting and auto-discharge in a 1.0 mm × 1.0 mm package - making it the only option among the three suitable for space-constrained, sequenced-power portable systems requiring both fast turn-off and controlled startup.
Availability
TCR3DM135,LF(SE) is available at Aetrix Electronics and suitable for smartphone baseband power, wearable sensor hub supply, and IoT edge node PMIC subsystems requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.
Supply support for TCR3DM135,LF(SE) includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Toshiba Electronic Devices & Storage Corporation is a global semiconductor manufacturer specializing in power management, logic, memory, and discrete devices, with core expertise in CMOS analog and mixed-signal IC design.
The TCR3DM series was developed specifically for ultra-compact, high-efficiency power delivery in portable consumer electronics - emphasizing low noise, fast transient response, and minimal board footprint without compromising protection features.
FAQ
What is the guaranteed output voltage tolerance for TCR3DM135,LF(SE)?
The TCR3DM135,LF(SE) guarantees output voltage accuracy of ±18 mV at 1.35 V output under nominal conditions (IOUT = 50 mA, Tj = 25°C). This tight tolerance ensures reliable operation of 1.35 V I/O interfaces without external trimming or calibration, and is specified across the full operating temperature range (-40°C to +85°C) per the datasheet's electrical characteristics table.
Does TCR3DM135,LF(SE) require external compensation components?
No, the TCR3DM135,LF(SE) is internally compensated and operates stably with only 1.0 μF ceramic capacitors on both VIN and VOUT pins. The datasheet explicitly confirms compatibility with low-ESR ceramics (recommended ESR < 10 Ω) and provides layout guidance - including placing COUT within 2 mm of the VOUT pin - to maintain phase margin and avoid oscillation.
How does the inrush current protection circuit function in TCR3DM135,LF(SE)?
The inrush current protection circuit in TCR3DM135,LF(SE) actively limits peak input current during power-up by controlling the slew rate of the pass transistor gate drive. This prevents large inrush spikes into the output capacitor, avoiding input rail collapse and reducing stress on upstream power sources - a feature confirmed in the product overview and functional description sections of the official Toshiba datasheet.
Can the thermal pad on the TCR3DM135,LF(SE) DFN4E package be left floating?
No, the center thermal pad on the TCR3DM135,LF(SE) DFN4E package must be soldered to a PCB GND plane. The datasheet specifies this connection as mandatory for both thermal performance (to meet 420 mW power dissipation rating) and electrical stability. Leaving it unconnected degrades thermal resistance by >50% and may cause premature thermal shutdown under load.
What is the minimum input voltage required for TCR3DM135,LF(SE) to regulate at full 300 mA?
The minimum input voltage for TCR3DM135,LF(SE) to sustain 300 mA output is calculated as VOUT + VDO(max) = 1.35 V + 520 mV = 1.87 V. Per the datasheet's dropout voltage table, the maximum dropout at 1.35 V output and 300 mA is 520 mV. Therefore, VIN must be ≥1.87 V to maintain regulation under full load across temperature and process variation.
TCR3DM135,LF(SE Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Toshiba Semiconductor and Storage
- Series:
- -
- Package/Case:
- 4-UDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Output Configuration:
- Positive
- Output Type:
- Fixed
- Number of Regulators:
- 1
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 1.35V
- Voltage - Output (Max):
- -
- Voltage Dropout (Max):
- 0.52V @ 300mA
- Current - Output:
- 300mA
- Current - Quiescent (Iq):
- -
- Current - Supply (Max):
- -
- PSRR:
- -
- Control Features:
- Enable
- Protection Features:
- Over Current, Over Temperature
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 4-DFN (1x1)
TCR3DM135,LF(SE FAQ
1.How can I place an order for TCR3DM135,LF(SE through Aetrix?
Please submit a Request for Quotation (RFQ) for TCR3DM135,LF(SE on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TCR3DM135,LF(SE reliable?
The price and inventory of TCR3DM135,LF(SE are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TCR3DM135,LF(SE is usually 5 days.
3.What payment methods are accepted for TCR3DM135,LF(SE?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TCR3DM135,LF(SE transactions.
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4.How is shipping managed for TCR3DM135,LF(SE?
TCR3DM135,LF(SE orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TCR3DM135,LF(SE order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TCR3DM135,LF(SE?
For technical support, including TCR3DM135,LF(SE datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TCR3DM135,LF(SE requirements.
6.How does Aetrix verify that TCR3DM135,LF(SE is sourced from the original manufacturer or authorized distributors?
All TCR3DM135,LF(SE products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TCR3DM135,LF(SE meets industry standards.
7.What is the process for return or replacement of TCR3DM135,LF(SE?
All TCR3DM135,LF(SE units undergo pre-shipment inspection (PSI). If there is an issue with TCR3DM135,LF(SE, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TCR3DM135,LF(SE part is unused and in its original packaging.
Return procedure for TCR3DM135,LF(SE:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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