NXP Semiconductors TDA8035HN/C1/S1QL
- Part No.:
- TDA8035HN/C1/S1QL
- Manufacturer:
- NXP Semiconductors
- Category:
- Specialized
- Package:
- 32-VFQFN Exposed Pad
- Datasheet:
-
TDA8035HN/C1/S1QL.pdf
- Description:
- IC INTFACE SPECIALIZED 32HVQFN
- Quantity:
- Payment:

- Shipping:

Inventory:3,338
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Product details
Overview
TDA8035HN/C1/S1QL from NXP Semiconductors is a highly integrated, low-power smart card interface IC designed for ISO/IEC 7816-compliant contact smart card readers. It delivers regulated 5 V / 3 V / 1.8 V card supply (VCC), supports up to 20 MHz card clock generation, provides thermal/short-circuit protection on all card contacts, and achieves ≤0.1 µA deep shutdown current - enabling power-efficient Pay TV and banking card readers.
For engineers reviewing the TDA8035HN/C1/S1QL datasheet, TDA8035HN/C1/S1QL pinout, TDA8035HN/C1/S1QL application, or TDA8035HN/C1/S1QL equivalent, this page details its HVQFN32 package integration, triple-voltage smart card power delivery, fault-aware activation/deactivation sequencing, and ISO 7816-3 timing compliance for secure embedded reader designs.
Technical Context
The TDA8035HN/C1/S1QL implements a dual-domain architecture: VDDP (2.7–5.5 V) powers an internal DC-to-DC converter that generates precise 5 V / 3 V / 1.8 V ±5 % VCC outputs, while VDD(INTF) (1.6–3.6 V) supplies the host interface logic. Its digital sequencer executes hardware-triggered activation/deactivation with controlled rise/fall times and built-in 4.05 ms PRESN debouncing.
Card interface protection includes per-contact thermal shutdown, ESD tolerance >8 kV HBM on card pins, and filtered overload detection at ~125 mA. Clock generation uses either external XTAL1 input or crystal oscillator (XTAL1/XTAL2), with synchronous CLKDIV1/CLKDIV2-controlled division (fXTAL, /2, /4, /8) ensuring 45–55 % duty cycle and no pulse distortion during frequency transitions.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Output Options | 5 V / 3 V / 1.8 V ±5 %, each supporting full ISO 7816 current load (65 mA @ 5 V/3 V, 35 mA @ 1.8 V) |
| Deep Shutdown Current | ≤0.1 µA - enables battery-backed or ultra-low-power portable card readers |
| Card Clock Frequency | Up to 20 MHz via programmable divider (fXTAL, /2, /4, /8) with synchronous switching and 45–55 % duty cycle guarantee |
| ESD Protection | >8 kV HBM on I/O, RST, VCC, AUX1, CLK, AUX2, PRESN - meets EMV-level robustness for payment terminals |
| Supply Supervision | Internally fixed thresholds for VDDP (2.25 V) and VREG (1.45 V); externally adjustable VDD(INTF) threshold via PORADJ resistor bridge |
| Package | HVQFN32 (SOT617-7), 5 × 5 × 0.85 mm, thermal-enhanced - supports high-density PCB layouts with 55 K/W junction-to-ambient (with 4 vias) |
| Compliance | Fully compliant with ISO/IEC 7816-3, NDS, and EMV 4.3 (C2 version); C1 version supports Pay TV and ID applications |
Pinout & Package
HVQFN32 (SOT617-7) package: 5 mm × 5 mm body, 0.85 mm height, 32-terminal no-lead thermally enhanced quad flat design with exposed thermal pad.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDDP (Pin 18) | Main power supply input | Accepts 2.7–5.5 V to feed DC-to-DC converter; enables VCC generation independent of host interface voltage |
| VDD(INTF) (Pin 4) | Host interface supply | Provides 1.6–3.6 V domain for CS, RSTIN, CLKDIV1/2, OFFN, and I/OUC - isolates host logic from card power domain |
| VCC (Pin 22) | Smart card supply output | Delivers regulated 5 V / 3 V / 1.8 V to card contact C1; decoupled by two 220 nF MLCCs (low ESR <100 mΩ) |
| RST (Pin 23) | Card reset output | Active-HIGH signal to card contact C2; synchronized to activation sequence with precise timing (t5 = t1 + 13T) |
| CLK (Pin 24) | Card clock output | Drives contact C3 at up to 20 MHz; duty cycle guaranteed 45–55 %; supports external clock injection or crystal oscillation |
| PRESN (Pin 30) | Card presence input | Active-LOW mechanical switch sense with integrated 4.05 ms debounce - eliminates false insertion/removal triggers |
| OFFN (Pin 10) | Fault interrupt output | Open-drain NMOS output (10 kΩ pull-up to VDD(INTF)) signaling short-circuit, overheating, or card removal during session |
Key Features
| Feature | Design Value |
|---|---|
| Triple-voltage VCC regulation | Single IC supports 5 V, 3 V, and 1.8 V smart cards without external LDOs - reduces BOM count and layout area |
| Hardware-triggered activation | Automatic, sequenced power-up (VCC ramp, CLK enable, RST assert) initiated solely by CMDVCCN falling edge - eliminates firmware dependency |
| Integrated DC-to-DC converter | Configurable as doubler/tripler/follower based on VDDP and target VCC - enables operation from single 3.3 V or 5 V rail |
| Three protected bidirectional I/O lines | I/O, AUX1, AUX2 (C7, C4, C8) with 15 mA current limiting, 1.5 MHz max data rate, and active pull-up (>1 mA @ 0.9 VCC) |
| EMV-ready fault handling | Simultaneous monitoring of VCC short, card removal, VDDP/VREG drop, and overtemperature - triggers emergency deactivation within microseconds |
Applications
| Pay TV Conditional Access | Banking Card Reader |
|---|---|
Use Scenario: Secure decryption of encrypted broadcast streams using conditional access modules (CAMs) inserted into set-top boxes. IC Role / Device Role / Timing Role: Provides regulated 3 V or 5 V power, precise CLK timing (ISO 7816-3), and RST control to CAM; manages hot-plug detection and fault-safe deactivation. Use Value: Enables <100 µA standby current and <90 µs deactivation time - critical for always-on STB power budgets and seamless channel switching. | Use Scenario: Embedded PIN entry devices (PEDs) and point-of-sale (POS) terminals reading EMV-compliant bank cards. IC Role / Device Role / Timing Role: Delivers 5 V/3 V/1.8 V VCC, synchronizes CLK/RST/I/O with host MCU, and detects card removal mid-transaction to prevent data corruption. Use Value: Built-in >8 kV HBM ESD protection and 125 mA overload detection eliminate need for external TVS diodes - reducing component count and validation effort. |
| Electronic Identity (eID) | Government ID Card Terminal |
Use Scenario: National ePassport and eID card readers in border control kiosks and citizen service centers. IC Role / Device Role / Timing Role: Supplies stable 3 V to contact chip; enforces strict ISO 7816-3 timing (tdeact = 35–250 µs); handles card presence debouncing and thermal faults. Use Value: Deep shutdown current ≤0.1 µA extends battery life in portable eID verifiers; HVQFN32 footprint allows compact, ruggedized enclosure design. | Use Scenario: High-reliability government-issued ID card enrollment and verification stations. IC Role / Device Role / Timing Role: Manages dual-voltage card support (5 V legacy, 3 V modern), performs automatic activation/deactivation, and signals faults via OFFN to host controller. Use Value: Compliance with ISO/IEC 7816 and NDS standards ensures interoperability with national ID schemes; thermal protection prevents field failures in unventilated enclosures. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar smart card interface applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SLB9670 | Trusted Platform Module (TPM) with integrated secure crypto engine; lacks dedicated VCC regulation and ISO 7816 analog front-end | Designed for PC platform security, not direct smart card reader replacement; requires external level shifters and regulators | Select only if cryptographic acceleration and secure boot attestation are required alongside card interface - not a functional substitute for TDA8035HN/C1/S1QL |
| TDA8024HN | Predecessor IC; supports only 5 V card supply; higher active current (12 mA typical); no 1.8 V mode or deep shutdown (<1 µA) | Limited to legacy 5 V-only cards; unsuitable for modern low-voltage eID or banking cards requiring 1.8 V | Choose only for backward-compatible upgrades where 5 V-only operation and higher power consumption are acceptable |
Compared with SLB9670 and TDA8024HN, the TDA8035HN/C1/S1QL uniquely integrates triple-voltage regulation, sub-µA deep shutdown, and hardware-sequenced activation - making it the only option for new designs targeting EMV 4.3, eID, and battery-powered Pay TV readers.
Availability
TDA8035HN/C1/S1QL is available at Aetrix Electronics and suitable for Pay TV conditional access modules, banking POS terminals, and government eID card readers requiring stable component supply, long-term lifecycle support, and ISO 7816-3 timing compliance.
Supply support for TDA8035HN/C1/S1QL includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications, with core expertise in smart card, NFC, and trusted execution technologies.
The TDA8035 belongs to NXP's contact smart card reader IC product line, engineered specifically to replace legacy readers with lower power, higher integration, and enhanced security - targeting EMV, eID, and Pay TV markets demanding certified, production-ready interfaces.
FAQ
What is the primary function of the TDA8035HN/C1/S1QL in a smart card system?
The TDA8035HN/C1/S1QL serves as a fully integrated smart card interface IC that generates regulated 5 V / 3 V / 1.8 V supply (VCC) for contact cards, provides ISO 7816-compliant CLK and RST signals, manages card presence detection, and executes hardware-controlled activation/deactivation sequences. Its role is to replace discrete regulator, level shifter, and timing logic circuits - directly interfacing between host microcontroller and card contacts while enforcing safety and timing requirements defined in ISO/IEC 7816-3. The TDA8035HN/C1/S1QL is optimized for reliability and low power in commercial and government-grade readers.
Does the TDA8035HN/C1/S1QL support 1.8 V smart cards, and how is voltage selection controlled?
Yes, the TDA8035HN/C1/S1QL supports 1.8 V smart cards via dedicated EN_1.8VN pin (Pin 8). When EN_1.8VN is driven LOW and EN_5V/3VN (Pin 7) is HIGH, the internal DC-to-DC converter configures for 1.8 V output on VCC (Pin 22). This selection is hardware-controlled and does not require firmware configuration. The device guarantees ±5 % regulation at 1.8 V with up to 35 mA continuous current and includes filtered overload detection at ~125 mA - meeting ISO 7816-3 requirements for low-voltage card operation. The TDA8035HN/C1/S1QL thus enables single-design compatibility across legacy 5 V, standard 3 V, and modern 1.8 V cards.
What is the significance of the OFFN pin on the TDA8035HN/C1/S1QL, and how is it used in fault handling?
The OFFN pin (Pin 10) is an open-drain NMOS interrupt output that signals fault conditions during active card sessions. It goes LOW upon detection of VCC short-circuit, card removal, VDDP/VREG supply drop, or overheating - triggering immediate emergency deactivation. OFFN remains LOW until the host sets CMDVCCN HIGH and completes full deactivation; its state then reflects card presence (HIGH = card inserted, after debounce). With internal 10 kΩ pull-up to VDD(INTF), OFFN enables simple GPIO monitoring without external components. In the TDA8035HN/C1/S1QL, OFFN is central to fail-safe operation - ensuring transaction integrity and preventing hardware damage in real-world reader deployments.
How does the TDA8035HN/C1/S1QL achieve ultra-low power consumption in standby mode?
The TDA8035HN/C1/S1QL achieves ultra-low standby power through two hierarchical modes: Shutdown mode (≤500 µA) and Deep Shutdown mode (≤0.1 µA). Deep Shutdown is entered by holding CMDVCCN HIGH while driving both EN_5V/3VN and EN_1.8VN LOW - disabling all voltage generators, oscillators, and card interfaces except the PRESN sense path. In this state, OFFN mirrors PRESN, allowing host wake-up on card insertion. The TDA8035HN/C1/S1QL maintains this sub-µA draw without external circuitry, making it ideal for battery-powered readers where multi-year operation is required. No additional power switches or controllers are needed to reach this level of efficiency.
Is the TDA8035HN/C1/S1QL pin-compatible with earlier NXP smart card ICs like the TDA8024?
The TDA8035HN/C1/S1QL is software-compatible with the TDA8024 and TDA8034 but not pin-compatible. While it retains identical register mapping and command protocol for host firmware reuse, the TDA8035HN/C1/S1QL uses a 32-pin HVQFN32 package (SOT617-7) versus the TDA8024's 28-pin SOIC or TSSOP. Key pin additions include EN_1.8VN (Pin 8), CLKDIV2 (Pin 6), and dedicated DC-to-DC capacitor terminals (SAM, SBM, SBP, SAP, VUP). Therefore, migrating from TDA8024 requires PCB layout revision to accommodate the larger HVQFN32 footprint and updated passive component placement - though firmware integration remains straightforward due to SW compatibility.
TDA8035HN/C1/S1QL Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- 32-VFQFN Exposed Pad
- Packaging:
- Tray
- Product Status:
- Active
- Applications:
- -
- Interface:
- Analog
- Voltage - Supply:
- 2.7V ~ 5.5V
- Supplier Device Package:
- 32-HVQFN (5x5)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
TDA8035HN/C1/S1QL FAQ
1.How can I place an order for TDA8035HN/C1/S1QL through Aetrix?
Please submit a Request for Quotation (RFQ) for TDA8035HN/C1/S1QL on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TDA8035HN/C1/S1QL reliable?
The price and inventory of TDA8035HN/C1/S1QL are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TDA8035HN/C1/S1QL is usually 5 days.
3.What payment methods are accepted for TDA8035HN/C1/S1QL?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TDA8035HN/C1/S1QL transactions.
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4.How is shipping managed for TDA8035HN/C1/S1QL?
TDA8035HN/C1/S1QL orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TDA8035HN/C1/S1QL order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TDA8035HN/C1/S1QL?
For technical support, including TDA8035HN/C1/S1QL datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TDA8035HN/C1/S1QL requirements.
6.How does Aetrix verify that TDA8035HN/C1/S1QL is sourced from the original manufacturer or authorized distributors?
All TDA8035HN/C1/S1QL products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TDA8035HN/C1/S1QL meets industry standards.
7.What is the process for return or replacement of TDA8035HN/C1/S1QL?
All TDA8035HN/C1/S1QL units undergo pre-shipment inspection (PSI). If there is an issue with TDA8035HN/C1/S1QL, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TDA8035HN/C1/S1QL part is unused and in its original packaging.
Return procedure for TDA8035HN/C1/S1QL:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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