STMicroelectronics TDA8139

Overview

TDA8139 from STMicroelectronics is a monolithic dual positive voltage regulator IC providing a fixed 5.1 V ±2% output (up to 750 mA) and an adjustable 2.8–16 V output (up to 750 mA), with integrated reset generation on OUTPUT1 and TTL-compatible disable control on OUTPUT2. It operates from 7–18 V input, features 1.4 V dropout at full load, and includes short-circuit and thermal protection. Used in multi-rail power management for legacy industrial controllers and analog signal processing systems.

For engineers reviewing the TDA8139 datasheet, TDA8139 pinout, TDA8139 application, or TDA8139 equivalent, key selection considerations include its dual-output architecture with independent enable/reset logic, Darlington-based low-dropout regulation, reset threshold hysteresis (20–75 mV), and SIP9/DIP16 package thermal resistance (9 °C/W and 15 °C/W junction-to-case respectively).

Technical Context

The TDA8139 integrates two independent linear regulators sharing a trimmed zener reference (2.5 V at PROGRAM pin), where OUTPUT1's 5.1 V is precision-fixed and OUTPUT2's voltage is set externally via R1/R2 divider. The reset circuit monitors OUTPUT1 voltage and triggers a delayed low-active pulse when VO1 falls below VO1RST (K − 0.25 V typical), with delay controlled by external capacitor Ce (e.g., 100 nF → 25 ms).

OUTPUT2 disable is TTL-level compatible (VDISL ≤ 0.8 V, VDISH ≥ 2 V), and both outputs employ Darlington pass transistors enabling 1.4 V dropout at 750 mA. Thermal shutdown activates at TJ = 145 °C, and short-circuit protection limits current to 1.6 A (VIN1 = 7 V) with safe permanent operation guaranteed up to 16 V input.

Key Specifications

Pinout & Package

Available in SIP9 (plastic single in-line, 9-pin) and DIP16 (dual in-line, 16-pin) packages. Tab connected to GROUND in SIP9; all GROUND pins (pins 3, 4, 5, 6, 7, 8, 10, 11, 12, 13, 14, 15, 16) tied internally in DIP16 variant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-output linear regulator applications.

Compared with LM2678-5.0/NOPB and TPS7A4700RGWR, the TDA8139 uniquely integrates fixed + adjustable linear regulation, reset generation, and TTL disable in one SIP9/DIP16 package-enabling compact, sequenced dual-rail power without external timing or logic components.

Availability

TDA8139 is available at Aetrix Electronics and suitable for industrial PLC I/O modules, analog sensor signal conditioning, and legacy broadcast equipment requiring stable component supply and long-lifecycle support.

Supply support for TDA8139 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing silicon solutions for automotive, industrial, and consumer markets since 1987.

The TDA8139 belongs to ST's legacy linear regulator product line, developed for robust multi-rail power management in industrial control and analog signal chain applications where integration, reliability, and predictable thermal behavior are prioritized over switching efficiency.

FAQ

What is the minimum input voltage required for stable 5.1 V output at 750 mA?

The TDA8139 requires ≥ 6.5 V input to sustain 5.1 V output at 750 mA, based on its 1.4 V dropout specification. Operation below 7 V is possible only at reduced load; the absolute minimum input is 7 V per datasheet limits to ensure full functionality including reset and disable behavior.

Can OUTPUT2 be used without connecting INPUT2?

Yes-OUTPUT2 can be powered solely from INPUT1. The datasheet confirms INPUT2 is optional; when left unconnected, OUTPUT2 draws current from INPUT1. However, using INPUT2 enables independent input domains, improving noise isolation between rails in sensitive analog designs.

How is the reset delay time calculated, and what capacitor value yields 100 ms?

Reset delay tRD = (Ce × 2.5 V) / 10 µA. For tRD = 100 ms, Ce = (100 ms × 10 µA) / 2.5 V = 400 nF. Standard values like 470 nF yield ~118 ms. The delay starts after OUTPUT1 recovers above VO1RST and ends when Ce charges to 2.5 V.

Is the TDA8139 RoHS-compliant and available in ECOPACK® packaging?

Yes-the TDA8139 is offered in environmentally friendly ECOPACK® packages compliant with RoHS Directive 2011/65/EU. Package markings and ordering codes (e.g., TDA8139TR) indicate lead-free finish; full compliance documentation is available in ST's ECOPACK® database at www.st.com.