Texas Instruments TDES9640RURR
- Part No.:
- TDES9640RURR
- Manufacturer:
- Texas Instruments
- Category:
- Serializers, Deserializers
- Package:
- 88-VFQFN Exposed Pad
- Datasheet:
-
TDES9640RURR.pdf
- Description:
- DESERIALIZER
- Quantity:
- Payment:

- Shipping:

Inventory:2,500
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Product details
Overview
TDES9640RURR from Texas Instruments is a V3Link deserializer hub IC that aggregates ultra-high-speed video data from up to four 7.55 Gbps sensors over coaxial or STP cables, delivers dual MIPI CSI-2 D-PHY/C-PHY outputs (up to 10 Gbps/port) and one D-PHY replication port, and supports 8-MP+ imaging in automotive-grade industrial vision systems.
For engineers reviewing the TDES9640RURR datasheet, TDES9640RURR pinout, TDES9640RURR application, or TDES9640RURR equivalent, key selection considerations include V3Link forward-channel rate (7.55 Gbps), MIPI output configuration (2× D-PHY/C-PHY + 1× D-PHY replication), VC-ID remapping support, PoC capability, and -20°C to 85°C operating range.
Technical Context
The TDES9640RURR implements a quad-channel V3Link receiver with adaptive equalization and bidirectional 47.1875 Mbps control channel, enabling robust long-cable sensor aggregation. It integrates configurable MIPI D-PHY v2.1 (4 lanes/port, 2.5 Gbps/lane) and C-PHY v1.1 (4 trios/port, 5.7 Gbps/trio) transmitters for flexible downstream processor interfacing.
Its architecture supports virtual channel interleaving across two primary CSI-2 ports plus a dedicated D-PHY replication port, with full VC-ID remapping and frozen-frame detection. The device includes dual I²C masters, 10 GPIOs for sensor sync/diagnostics, and CMLOUT replication of all four V3Link RX inputs for cascaded deserialization.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Forward Channel Rate | 7.55 Gbps per link - enables 8-MP+ image sensor aggregation over single coax/STP cable |
| MIPI Output Ports | 2× configurable D-PHY/C-PHY + 1× D-PHY-only replication port - supports multi-sensor routing and redundancy |
| D-PHY Lane Capacity | Up to 4 lanes × 2 clocks per port, 2.5 Gbps/lane - delivers up to 10 Gbps per CSI-2 port |
| C-PHY Trio Capacity | Up to 4 trios per port, 5.7 Gbps/trio - delivers up to 22.8 Gbps per CSI-2 port in C-PHY mode |
| Operating Temperature | -20°C to 85°C - qualified for industrial machine vision and surveillance environments |
| Power-over-Coax | Supported - eliminates separate power wiring for remote sensor modules |
| Virtual Channels | 16 VC IDs with remapping - enables time-division multiplexing of multiple sensors/exposures per port |
Pinout & Package
VQFNP (RUR) 88-pin package, 12.00 mm × 12.00 mm body, 0.5 mm pitch, 0.9 mm max height, wettable flank compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CLKIN_0–3 | V3Link reference clock input | Accepts 7.55/3.775/1.8875 Gbps serial data with embedded clock recovery |
| CSI0_P/N–CSI1_P/N | MIPI D-PHY/C-PHY differential output pairs | Drive downstream SoC CSI-2 receivers; configurable per port for D-PHY or C-PHY signaling |
| CSI2_P/N | D-PHY-only replication port output | Provides mirrored copy of CSI0 output for diagnostic or redundant processing paths |
| GPIO0–9 | General-purpose I/O | Support sensor synchronization pulses, status reporting, and diagnostics via programmable interrupt (INTB) |
| I2C_SCL0/SDA0, I2C_SCL1/SDA1 | Dual I²C master interfaces | Configure connected serializers (e.g., TSER9615) and monitor health status independently |
Key Features
| Feature | Design Value |
|---|---|
| Quad V3Link RX with auto-equalization | Compensates for cable loss up to 15 m coax or 20 m STP at 7.55 Gbps without manual tuning |
| VC-ID remapping & 16 virtual channels | Enables dynamic assignment of sensor streams to specific virtual channels for seamless multi-exposure or multi-modal capture |
| Frozen frame detection | Hardware-level monitoring triggers interrupt on video stall, enabling fail-safe system response in safety-critical vision applications |
| CMLOUT replication ports | Four independent CMOS-level outputs replicate each V3Link RX channel, allowing daisy-chained deserializer topologies |
| Low-power sleep with GPIO retention | Maintains GPIO state during sleep mode, preserving sensor sync context without host reinitialization |
Applications
| Video Surveillance | Industrial Robots |
|---|---|
Use Scenario: Multi-camera high-resolution perimeter monitoring with synchronized night/day imaging. IC Role / Device Role / Timing Role: Deserializer hub aggregating four 8-MP sensors over coax, delivering time-aligned CSI-2 streams to edge AI processor. Use Value: Enables single-SoC ingestion of four ultra-HD video feeds with VC-ID separation and PoC simplification. | Use Scenario: Real-time 3D vision-guided robotic arm control using stereo + depth + thermal sensors. IC Role / Device Role / Timing Role: Central deserializer synchronizing heterogeneous sensor timing via GPIO-triggered exposure and frozen-frame fault detection. Use Value: Guarantees deterministic latency and stream integrity across mixed-sensor modalities under factory EMI conditions. |
| Machine Vision | Patient Monitoring |
Use Scenario: High-speed automated optical inspection (AOI) of PCBs with multi-angle lighting and trigger-based capture. IC Role / Device Role / Timing Role: Aggregating four synchronized line-scan or area-scan imagers into dual CSI-2 ports with VC remapping per inspection zone. Use Value: Eliminates frame drops during rapid motion by leveraging hardware VC arbitration and D-PHY lane scaling. | Use Scenario: Compact endoscopic imaging module with integrated illumination and multi-spectral sensing. IC Role / Device Role / Timing Role: Deserializer hub supporting miniaturized camera head with PoC, low-power sleep, and diagnostic GPIOs for clinical alerts. Use Value: Reduces cabling complexity and power delivery overhead while maintaining medical-grade reliability via built-in data integrity checks. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar deserializer hub applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TSER9615 | Serializer companion (not deserializer); requires pairing with TDES9640RURR for full link operation | Used on sensor side only; cannot replace TDES9640RURR's aggregation or CSI-2 output functions | Select TSER9615 only as upstream serializer when building complete V3Link camera module with TDES9640RURR |
| MAX96712 | 10-bit GMSL2 deserializer with 6 Gbps max rate, single CSI-2 port, no C-PHY support | Limited to three sensors, lower bandwidth, no VC-ID remapping or replication port | Choose MAX96712 for cost-sensitive GMSL2-based designs where 7.55 Gbps and dual CSI-2 ports are not required |
Compared with TSER9615 (a serializer) and MAX96712 (a lower-bandwidth GMSL2 deserializer), the TDES9640RURR uniquely provides quad-link 7.55 Gbps aggregation, dual configurable MIPI CSI-2 outputs with replication, and full VC-ID remapping-making it the only solution for 8-MP+ multi-sensor systems requiring V3Link compatibility and C-PHY/D-PHY flexibility.
Availability
TDES9640RURR is available at Aetrix Electronics and suitable for video surveillance, industrial robotics, and machine vision applications requiring stable component supply, long-cable sensor connectivity, and MIPI CSI-2 interface scalability.
Supply support for TDES9640RURR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor company specializing in analog, embedded processing, and connectivity technologies, with leadership in automotive, industrial, and communications markets.
The TDES9640RURR belongs to TI's V3Link Enhanced Vision product line, designed specifically for ultra-high-resolution, multi-sensor camera systems in harsh industrial and safety-critical environments.
FAQ
What is the maximum cable length supported by the TDES9640RURR at 7.55 Gbps?
The TDES9640RURR supports up to 15 meters over 75-Ω coaxial cable and up to 20 meters over shielded twisted-pair (STP) at 7.55 Gbps, enabled by its adaptive receiver equalization circuitry. This performance is validated per TI's SNLS744A datasheet and applies to standard RG-174 or equivalent coax and AWG26 STP. Cable quality, shielding integrity, and connector choice directly impact achievable length.
Does the TDES9640RURR support both MIPI D-PHY and C-PHY simultaneously on its output ports?
No - the TDES9640RURR supports either D-PHY or C-PHY per output port, but not both simultaneously. CSI Port 0 and CSI Port 1 can be independently configured as D-PHY v2.1 or C-PHY v1.1 in the device register map; CSI Port 2 is D-PHY only. Configuration is static per power-on initialization and requires matching downstream SoC PHY support.
Can the TDES9640RURR operate without an external crystal or reference clock?
Yes - the TDES9640RURR recovers clock embedded in the V3Link serial data stream and does not require an external crystal or reference clock. Its PLL-based clock data recovery (CDR) circuit locks to incoming 7.55/3.775/1.8875 Gbps signals, eliminating clock distribution complexity and jitter accumulation in multi-sensor systems.
How many virtual channels does the TDES9640RURR support, and how is VC-ID remapping implemented?
The TDES9640RURR supports 16 virtual channels with full VC-ID remapping capability. Remapping is performed in hardware via register-programmable lookup tables that assign incoming sensor stream IDs to specific VC numbers on each CSI output port. This allows dynamic reassignment of sensor sources to different virtual channels without software intervention or frame buffering delay.
Is Power-over-Coax (PoC) supported on all four V3Link input channels of the TDES9640RURR?
Yes - PoC is supported on all four V3Link input channels (CLKIN_0 through CLKIN_3), enabling centralized power delivery to up to four remote sensor modules over the same coaxial cable carrying high-speed video data. Each channel supports up to 300 mA at 12 V, with independent overcurrent protection and telemetry reporting via the bidirectional control channel.
TDES9640RURR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 88-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Deserializer
- Data Rate:
- 7.55Gbps
- Input Type:
- V3Link
- Output Type:
- CSI-2, MIPI
- Number of Inputs:
- 4
- Number of Outputs:
- 5
- Voltage - Supply:
- -
- Operating Temperature:
- -20°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 88-VQFNP (12x12)
TDES9640RURR FAQ
1.How can I place an order for TDES9640RURR through Aetrix?
Please submit a Request for Quotation (RFQ) for TDES9640RURR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TDES9640RURR reliable?
The price and inventory of TDES9640RURR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TDES9640RURR is usually 5 days.
3.What payment methods are accepted for TDES9640RURR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TDES9640RURR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TDES9640RURR?
TDES9640RURR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TDES9640RURR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TDES9640RURR?
For technical support, including TDES9640RURR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TDES9640RURR requirements.
6.How does Aetrix verify that TDES9640RURR is sourced from the original manufacturer or authorized distributors?
All TDES9640RURR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TDES9640RURR meets industry standards.
7.What is the process for return or replacement of TDES9640RURR?
All TDES9640RURR units undergo pre-shipment inspection (PSI). If there is an issue with TDES9640RURR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TDES9640RURR part is unused and in its original packaging.
Return procedure for TDES9640RURR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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